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10-/12-bit, low power, broadband mxfe ad9961/AD9963 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features dual 10-bit/12-bit, 100 msps adc snr = 67 db, f in = 30.1 mhz dual 10-bit/12-bit, 170 msps dac aclr = 74 dbc 5 channels of analog auxiliary input/output low power, <425 mw at maximum sample rates supports full and half-duplex data interfaces small 72-lead lfcsp lead-free package applications wireless infrastructure picocell, femtocell basestations medical instrumentation ultrasound afe portable instrumentation signal generators, signal analyzers general description the ad9961/AD9963 are pin-compatible, 10-/12-bit, low power mxfe? converters that provide two adc channels with sample rates of 100 msps and two dac channels with sample rates to 170 msps. these converters are optimized for transmit and receive signal paths of communication systems requiring low power and low cost. the digital interfaces provide flexible clocking options. the transmit is configurable for 1, 2, 4, and 8 interpolation. the receive path has a bypassable 2 decimating low-pass filter. the ad9961 and AD9963 have five auxiliary analog channels. three are inputs to a 12-bit adc. two of these inputs can be configured as outputs by enabling 10-bit dacs. the other two channels are dedicated outputs from two independent 12-bit dacs. the high level of integrated functionality, small size, and low power dissipation of the ad9961/AD9963 make them well- suited for portable and low power applications. functional block diagram dllfilt dll and clock distribution ad9961/AD9963 clkp clkn txclk txiq/txnrx txd[11:0] trxclk trxiq trxd[11:0] reset sdio sclk cs lpf lpf lpf lpf mux temperature sensor internal serial port logic references and bias ldo vregs data assembler aux adc aux dac aux dac aux dac txip txin auxin1 auxio2 auxio3 12-bit dac txqp txqn 12-bit dac rxip rxin 12-bit adc rxqp rxqn dac12a aux dac dac12b 1/2 1/2 1/2/4/8 1/2/4/8 auxadcref refio txcml rxcml rxbias ldo_en 12-bit adc 08801-001 figure 1. product highlights 1. high performance with low power consumption. the dacs operate on a single 1.8 v to 3.3 v supply. transmit path power consumption is <100 mw at 170 msps. receive path power consumption is <350 mw at 100 msps from 1.8 v supply. sleep and power-down modes are provided for low power idle periods. 2. high integration. the dual transmit and dual receive data converters, five channels of auxiliary data conversion and clock generation offer complete solutions for many modem designs. 3. flexible digital interface. the interface mates seamlessly to most digital baseband processors. datasheet.in
ad9961/AD9963 rev . 0 | page 2 of 60 table of contents features .............................................................................................. 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 spec ifications ..................................................................................... 3 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configurations and function descriptions ........................... 9 typical performance characteristics ........................................... 13 terminology .................................................................................... 18 theory of operation ...................................................................... 19 serial control port .......................................................................... 20 general operation of serial control port ............................... 20 sub serial interface communications ..................................... 21 configuration registers ................................................................. 23 configuration register bit descriptions ................................. 24 rec eive path ..................................................................................... 35 receive adc operation ............................................................ 35 decimation filter and digital offset ....................................... 36 transmit path .................................................................................. 38 interpolation filters .................................................................... 38 transmit dac operation .......................................................... 40 transmit dac outputs ............................................................. 42 device clocking .............................................................................. 45 clock distribution ..................................................................... 45 driving the clock input ............................................................ 46 clock multiplication using the dll ....................................... 46 configuring the clock doublers .............................................. 47 digital interfaces ............................................................................ 48 trx port operation (full - duplex mode) ............................... 48 single adc mode ...................................................................... 48 tx port operation (full - duplex mode) ................................. 49 half - duplex mode ..................................................................... 50 auxiliary converters ...................................................................... 52 auxiliar y adc ............................................................................ 52 conversion clock ....................................................................... 52 auxiliary dac s........................................................................... 53 power supplies ................................................................................ 55 power supply configuration examples ................................... 55 po wer dissipation ....................................................................... 55 outline dimensions ....................................................................... 58 ordering guide .......................................................................... 58 revision history 7/ 10 revision 0: initial version datasheet.in
ad9961/AD9963 rev. 0 | page 3 of 60 specifications t min to t max , rx33v = txvdd = clk 33v = dr vdd = aux33v = 3.3 v. all ldos e nabled, i outfs = 2 ma, dac s ample r ate = 125 msps . no i nterpolation, unless otherwise noted . table 1 . tx path specifications ad9961 AD9963 parameter min typ max min typ max unit txdac dc c haracteristics resolution 10 12 bits differential nonlinearity 0.1 0. 3 lsb gain variation (internal reference) ?10 0.4 +10 ?10 0.4 +10 %fsr gain matching ?2.4 0.4 +2.4 ?2.4 0.4 +2.4 %fsr offset error ?0.03 +0.03 ?0.03 +0.03 %fsr full - scale output current (default setting) 2.0 2.0 ma output compliance range txvdd = 3.3 v, v txcml = 0 v ?0.5 +1.0 ?0 .5 +1.0 v txvdd = 3.3 v , v txcml = 0.5 v +0.7 +1.7 +0.7 +1.7 v txvdd = 1.8 v , v txcml = 0 v ?0.5 + 0.8 ?0.5 + 0.8 v offset temperature drift 0 0 ppm/c gain temperature drift (internal reference) 40 40 ppm/c tx reference (d e fau lt r egister s ettings ) internal reference voltage (refio) 1.02 1.02 v output resistance 10 10 k? temperature drift 25 25 ppm/c adjustment range (txvdd = 3 v) 0.8 1.2 0.8 1.2 v adjustment range (txvdd = 1.8 v) 0.8 refio 0.8 refio v txdac ac c haracteristics maximum update rate 175 175 msps spurious - free dynamic range f out = 5 mhz 78 81 dbc f out = 20 mhz 68 70 dbc two - tone intermodulation distortion f out1 = 5 mhz, f out2 = 6 mhz 85 89 dbc f out1 = 20 mhz, f out2 = 21 mhz 78 80 dbc noise spectral density f out = 5 mhz ?140 ?145 dbm/hz f out = 20 mhz ?136 ?141 dbm/hz w- cdma adjacent channel leakage ratio, 1 carrier f dac = 122.88 mhz, f out = 1 1 mhz 70 74 dbc tx path digital filter input rates srrc (8 interpolation mode) 21.875 21.875 mhz int0 (4 interpolation mode) 43.75 43.75 mhz int1 (2 interpolation mode 87.5 87.5 mhz transmit dac (1 interpolation mode) 175 175 mhz datasheet.in
ad9961/AD9963 rev . 0 | page 4 of 60 t min to t max , rx33v = txvdd = clk33v = drvdd = aux33v = 3.3 v. all ldos e nabled , adc sample r ate = 100 msps. no d ecimation, unless otherwise noted . table 2 . rx path specifications ad9961 ad996 3 parameter min typ max min typ max unit rx adc dc c haracteristics resolution 10 12 bits differential nonlinearity 0. 1 0. 3 lsb gain error 1 1 %fsr offset error 0.5 0.5 %fsr input voltage range 1.56 1.56 v p -p d iff input capacitance 8 8 pf rx adc ac s pecifications maximum sample rate 100 100 msps spurious free dynamic range f in = 10.1 mhz 77 77 dbc f in = 70.1 mhz 75 73 dbc two - tone intermodulation distortion f in1 = 10 mhz, f in2 = 11 mhz 78 82 dbc f in1 = 29 mhz, f in2 = 32 mhz 76 80 dbc signal -to - noise ratio f in = 10.1 mhz 61 68 dbfs f in = 30. 1 mhz 60 67 dbfs f in = 70.1 mhz 60 66 dbfs rxcml outputs output voltage 1.4 1.4 v output current 0.1 0.1 ma rx digital filter characteristics 2 decimation latency ( adc clock cycles) 49 49 cycles passband ri pple ; f out /f dac (0.4 f data ) 0.2 0.2 f out /f dac stop - band rejection (f data 0.4 f data ) 70 70 db datasheet.in
ad9961/AD9963 rev. 0 | page 5 of 60 t min to t max , rx33v = txvdd = clk33v = drvdd = aux33v = 3.3 v. all ldos e nabled , unless otherwise noted . table 3 . auxiliar y converter specifications ad9961 AD9963 units parameter min typ max min typ max a uxiliary dac12a/auxdac12b resolution 12 12 bits differential nonlinearity 0.8 0.8 lsb gain error 2.0 2.0 % settling time ( 1%) 1 1 s a uxi liary dac10a/dac10b (range = 0.5 v to 1.5 v) resolution 10 10 bits differential nonlinearity 1.0 1.0 lsb gain error 2.0 2.0 % settling time ( 1%) 10 10 s auxiliary adc resolution 12 12 bits differential nonli nearity ? 1.0 +1.0 ? 1.0 +1.0 lsb gain error (internal reference) ? 2.0 +2.0 ? 2.0 +2.0 % input voltage range 0 3.2 0 3.2 v maximum sample rate 50 50 khz datasheet.in
ad9961/AD9963 rev . 0 | page 6 of 60 f clk = 125 mhz, f dll = 250 mhz, da c sample r ate = 125 msps, adc sample r ate = 62.5 msps, u nless otherwise noted . table 4 . power consumption specifications ad9961 AD9963 parameter min typ max min typ max unit 1.8 v only operation ( external 1.8 v) clk33v 1.65 1.65 ma txvdd 10.7 10.7 ma drvdd 29.4 3 4.9 ma dvdd18v 21.0 22.7 ma clk18v 3.84 3.84 ma dll18v 9.98 9.98 ma rx18v 79.2 79.2 ma rx18vf 34.3 34.3 ma 3.3 v only operation ( on - chip regulators ) txvdd 12.1 12.1 ma clk33v 17.0 17.0 ma rx33v 113 113 ma drvdd 93 108 ma aux33v 0.55 0.55 ma supply voltage range clk33v , txvdd (these supplies must be tied t ogether) 1.72 3.63 1.72 3.63 v drvdd 1.72 3.63 1.72 3.63 v dvdd18v 1.72 1.89 1.72 1.89 v clk18v 1.72 1.89 1.72 1.89 v dll1 8v 1.72 1.89 1.72 1.89 v rx18v 1.72 1.89 1.72 1.89 v rx18vf 1.72 1.89 1.72 1.89 v rx 33 v 2.50 3.63 2.50 3.63 v au x 33 v (auxadc enabled) 3.14 3.63 3.14 3.63 v au x 33 v (auxadc disabled) 1.72 3.63 1.72 3.63 v datasheet.in
ad9961/AD9963 rev. 0 | page 7 of 60 table 5 . digital logic level specifications parameter conditions min typ max unit cmos input logic level v in logic high drvdd = 1.8 v 1.2 v v in logic high drvdd = 2.5 v 1.7 v v in logic high drvdd = 3.3 v 2.0 v v in logic low drvdd = 1.8 v 0.5 v v in logic low drvdd = 2.5 v 0.7 v v in logic low drvdd = 3.3 v 0.8 v cmos output logic level v out logic high drvdd = 1.8 v 1.35 v v out logic high drvdd = 2.5 v 2.05 v v out logic high drvdd = 3.3 v 2.4 v v out logic low drvdd = 1.8 v 0.4 v v out logic low drvdd = 2.5 v 0.4 v v out logic low drvdd = 3.3 v 0.4 v dac clock input differential peak -to - peak voltage 200 400 clk33v mv p -p d iff duty cycle 45 55 % slew rate 0.1 v/ns direct clocking clock rate clkp/clkn inpu ts 0.1 200 mhz dll enabled % clock rate dll delay line output 100 310 mhz serial peripheral interface maximum clock rate 50 mhz minimum pulse width high (t hi gh ) 10 ns minimum pulse width low (t low ) 10 ns setup time, sdi o (data i n) to sclk (t ds ) 5.0 ns hold time, sdi to sclk (t dh ) 5.0 ns data valid, sdio (data out) to sclk (t dv ) 5.0 ns setup time, cs to sclk (t s ) 5.0 ns datasheet.in
ad9961/AD9963 rev . 0 | page 8 of 60 absolute maximum ratings table 6 . parameter with re spect to rating rx33v, aux33v rxgnd ?0.3 v to +3.9 v txvdd txgnd ?0.3 v to +3.9 v drvdd dgnd ?0.3 v to +3.9 v clk33v epad ?0.3 v to +3.9 v rx18v, rx18vf rxgnd ? 0.3 to +2.1 v dvdd18v epad ? 0.3 to +2.1 v clk18v, dll18v epad ? 0.3 to +2.1 v rxgnd, txgnd, dgnd, epad ?0.3 v to +0.3 v txip , txin, txqp, txqn txgnd ?1.0 v to txvdd + 0.3 v rxip, rxin, rxqp, rxqn rxgnd ?0.3 v to rx18v + 0.3 v cs , sclk, sdio, dgnd reset , ldo _en ?0.3v to drvdd + 0.3 v trxd [11:0], txd[11:0 ] , txiq, trxiq, txclk, t rxclk dgnd ?0.3 v to drvdd + 0.3 v clkp, clkn epad ?0.3 v to clk33v + 0.3 v junction temperature +125c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect d evice reliability. t hermal resistance the exposed paddle must be soldered to the ground plane for the lfcsp package. soldering the exposed paddle to the customer board i n creases the reliability of the solder joints, maximizing the the r mal capability of the package. table 7 . thermal resistance airflow ja jb jc unit 1 m/ s ec 17.1 10.6 1.0 c/w 0 m/s ec 20.3 c/w typical ja , jb , and jc are specified for a jedec standard 51 - 7 high - thermal test board. airflow increases heat dis sipation, effectively reducing ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, r e duces the ja . esd caution datasheet.in
ad9961/AD9963 rev. 0 | page 9 of 60 pin configuration s and function descrip tion s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 aux33v auxadcref rxq p rxqn rxgnd rxbias rx18v rx33v rx18vf rxcm l rxgnd rxin rxi p ldo_en reset sclk 17cs 18sdio 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 dgnd dr vdd trxd9 trxd8 trxd7 trxd6 trxd5 trxd4 trxd3 trxd2 trxd1 trxd0 nc nc dr vdd dgnd 35 trxiq 36 trxclk 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 dllfi lt dll18v dvdd18 dr vdd nc nc txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 txd8 txd9 txiq/txnrx txclk 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 auxin1 auxio2 auxio3 dac12 a dac12b txvdd txin txip txgnd refio txcm l txvdd txqp txqn clk33v clk p clkn clk18v notes 1. exposed p ad must be soldered t o pcb. 2. nc = no connec t. pin 1 indic at or ad9961 (top view) 08801-002 figure 2 . ad9961 pin configuration table 8 . ad9961 pin function description s pin no. mnemonic description 1 aux33v analog supp ly for the auxiliary adc and auxiliary dacs (3.3 v 5 %, 1.8 v 5 % i f auxiliary adc is p owe red d own) . 2 auxadcref reference output ( or i nput) for auxiliary adc. 3, 4 rxqp, rxqn differential adc q inputs. the default full -s cale i nput v oltage r ange is 1.56 v p-p d ifferential . 5, 11 rxgnd receive path g round. 6 rxbias exte rnal bias resistor con nection. an optional 10 k? resistor can be connected between this pin and the analog ground to improve the accuracy of the full - scale ran g e of the r x adcs. 7 rx18v output of rx18v v oltage r egulator. 8 rx33v input to rx18v and rx18vf v oltage r egulators ( 2 .5 v to 3.3 v ). if ldos are not being used, short p in 8 to p in 7. 9 rx18vf output of rx18vf v oltage r egulator. 10 rxcml adc common - mode voltage output. 12, 13 rxin, rxip differential adc i inputs. the default f ull -s cale i nput v oltage r ange is 1.56 v p-p d ifferential . 14 ldo_en control pin for ldos (gnd = disable all ldos, float = enable dvdd18 ldo only, drvdd = enable all ldos) . 15 reset reset. active low to reset the configuration registers to default values and reset device. 16 sclk clock input for serial port. 17 cs active low chip select. 18 sdio bidirectional data line for serial port. 19, 34 dgnd digital c ore g round. 20, 33, 51 drvdd input/output pad r ing supply voltage (1.8 v to 3.3 v). 21 to 30 trxd 9 to trxd 0 adc output data in full duplex mode. adc output data and dac input data in h alf -d uplex m ode. 31, 32, 49, 50 nc not connected . 35 trxiq output s ignal i ndicating from w hich adc the o utput d ata i s s ourced. datasheet.in
ad9961/AD9963 rev . 0 | page 10 of 60 pin no. mnemonic description 36 trxclk qualifying c lock for the trxd b us. 37 txclk qualifying c lock for the txd b us. it c an be configured as either an input or output. 38 txiq/txnrx dual f unction p in. in half - duplex mode (txnrx) , this pin controls the direction of the trx port. in full - duplex mode (txiq) , this input signal in dicates to which dac, i or q, the txdac input d ata is intended. 39 to 48 txd 9 to txd 0 txdac input d ata. 52 dvdd18 digital core 1.8 v s upply. 53 dll18v output of dll18v v oltage r egulator. 54 dllfilt dll filter output . 55 clk18v output of clk18v v oltage r egulator. 56, 57 clkn, clkp differential input clock. 58 clk33v input to clk18v and dll18v v oltage r egulators ( 1.8 v to 3.3 v ). if ldos are not being used , short p in 58 to p in 55. clk33v must track txvdd. 59, 60 txqn, txqp complementary dac q current outputs. 61, 67 txvdd analog supply voltage for tx path ( 1.8 v to 3.3 v ). txvdd must track clk33v . 62 txcml common - mode input voltage for the i and q tx dacs. 63 refio decoupling p oint for internal dac 1.0 v bandgap reference. use a 0.1 f capacitor t o agnd. 64 txgnd transmit path g round. 65, 66 txip, txin complementary dac i current outputs. 68 dac12b auxiliary dac b output. 69 dac12a auxiliary dac a output. 70 auxio3 selectable a nalog p in. programmable to e ither input 3 of the a uxiliary adc or to the a uxiliary dac10b o utput. 71 auxio2 selectable a nalog p in. programmable to e ither input 2 of the a uxiliary adc or to the a uxiliary dac10a o utput. 72 auxin1 input 1 of a uxiliary adc. epad thermal pad u nder chip. this must be connected to agnd for proper chip operation. it provides both a thermal and electrical connection to the pcb. datasheet.in
ad9961/AD9963 rev. 0 | page 11 of 60 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 aux33v auxadcref rxq p rxqn rxgnd rxbias rx18v rx33v rx18vf rxcm l rxgnd rxin rxi p ldo_en reset sclk 17cs 18sdio 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 dgnd dr vdd trxd9 trxd8 trxd 11 trxd10 trxd7 trxd6 trxd5 trxd4 trxd3 trxd2 trxd1 trxd0 dr vdd dgnd 35 trxiq 36 trxclk 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 dllfi lt dll18v dvdd18 dr vdd txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 txd8 txd9 txd10 txd11 txiq/txnrx txclk 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 auxin1 auxio2 auxio3 dac12 a dac12b txvdd txin txip txgnd refio txcm l txvdd txqp txqn clk33v clk p clkn clk18v notes 1. exposed p ad must be soldered t o pcb. pin 1 indic at or AD9963 (top view) 08801-003 figure 3 . AD9963 pin configuration table 9. AD9963 pin function description s pin no. mnemonic description 1 aux 33v analog supp ly for the auxiliary adc and auxiliary dacs (3.3 v 10%, 1.8 v 10% i f auxiliary adc i s powered d own) . 2 auxadcref reference output (or input) for auxiliary adc. 3, 4 rxqp, rxqn differential adc q inputs. full - scale input voltage r ange i s 1.56 v p-p differential . 5, 11 rxgnd receive path g round. 6 rxbias exter nal bias resistor connec tion. this voltage is nominally 0.5 v. a 10 k? resistor can be connected between this pin and analog ground to improve the r x adc full - scale accuracy. 7 r x18v output of rx18v v oltage r egulator. 8 rx33v input to rx18v and rx18vf v oltage r egulators ( 2.5 v to 3.3 v ). if ldos are not being used , short p in 8 to p in 7. 9 rx18vf output of rx18vf v oltage r egulator. 10 rxcml adc common - mode voltage output. 12, 13 rxin, rxip differential adc i inputs. full -s cale input v oltage r ange is 1.56 v p-p d ifferential . 14 ldo_en control pin for ld os (gnd = disable all ldos, float = enable dvdd18 ldo only, drvdd = enable all ldos) . 15 reset reset. active low to reset the configuration registers to default values and reset device . 16 sclk clock input for serial port. 17 cs active low chip select. 18 sdio bidirectional data line for serial port. 19, 34 dgnd digital c ore g round. 20, 33, 51 drvdd input/output p ad r ing supply voltage (1.8 v to 3.3 v). 21 to 32 trxd 11 to trxd 0 adc output data in full duplex mode. adc output data and dac input data in h alf -d uplex m ode. 35 trxiq output s ignal indicating from w hich adc the o utput d ata i s sou rced. 36 trxclk qualifying c lock for the trxd b us. 37 txclk qualifying c lock for the txd b us. it c an be configured as either an input or output. 38 txiq/txnrx dual f unction p in. in half - duplex mode (txnrx), this pin controls the direction of the trx por t. in full - duplex mode (txiq) , this input signal indicates to which dac, i or q, the txdac input data is intended. 39 to 50 txd 11 to txd 0 txdac input d ata. 52 dvdd18 digital core 1.8 v s upply. 53 dll18v output of dll18v v oltage r egulator. datasheet.in
ad9961/AD9963 rev . 0 | page 12 of 60 pin no. mnemonic description 54 dllfilt dl l filter output. 55 clk18v output of clk18v v oltage r egulator. 56,57 clkn, clkp differential input clock. 58 clk33v input to clk18v and dll18v voltage regulators ( 1.8 v to 3.3 v). if ldos are not being used, short pin 58 to pin 55. clk33v must track tx vdd. 59, 60 txqn, txqp complementary dac q current outputs. 61, 67 txvdd analog supply voltage for tx path ( 1.8 v to 3.3v ). txvdd must track clk33v . 62 txcml common - mode input voltage for the i and q tx dacs. 63 refio decoupling p oint for internal dac 1.0 v bandgap reference. use a 0.1 f capacitor to agnd. 64 txgnd transmit p ath g round. 65, 66 txip, txin complementary dac i current output s. 68 dac12b auxiliary dac b output. 69 dac12a auxiliary dac a output. 70 auxio3 selectable a nalog p in. progr ammable to e ither input 3 of the a uxiliary adc or to the a uxiliary dac10b o utput. 71 auxio2 selectable a nalog p in. programmable to e ither input 2 of the a uxiliary adc or to the a uxiliary dac10a o utput. 72 auxin1 input 1 of a uxiliary adc. epad thermal p ad u nder chip. this must be connected to agnd for proper chip operation. it provides both a thermal and electrical connection to the pcb. datasheet.in
ad9961/AD9963 rev. 0 | page 13 of 60 typical performance characteristics 60 65 70 75 80 85 90 95 0 10 20 30 40 50 60 sfdr (dbc) f out (mhz) i fs = 1m a i fs = 2m a 08801-201 figure 4. second harmonic distortion vs. f out o ver f ull -s cale c urrent, f dac = 125 mhz, 1 , digital scale = 0 dbfs, txvdd = 1.8 v 50 55 60 65 70 75 80 85 90 0 10 20 30 40 50 60 sfdr (dbc) f out (mhz) i fs = 2m a i fs = 1m a 08801-202 figure 5 . third harmonic distortion vs. f out o ver f ull -s cale c urrent, f dac = 125 mhz, 1 , digital scale = 0 dbfs, txvdd = 1.8 v 50 55 60 65 70 75 80 85 90 95 100 0 10 20 30 40 50 60 sfdr (dbc) f out (mhz) i fs = 1m a i fs = 4m a i fs = 2m a 08801-203 figure 6. second harmonic distortion vs. f out o ver f ull -s cale c urrent, f dac = 125 mhz, 1 , digital scale = 0 dbfs, txvdd = 3.3 v 50 55 60 65 70 75 80 85 90 95 100 0 10 20 30 40 50 60 sfdr (dbc) f out (mhz) i fs = 1m a i fs = 4m a i fs = 2m a 08801-204 figure 7. third harmonic distortion vs. f out o ver f ull -s cale c urrent, f dac = 125 mhz, 1 , digital scale = 0 dbfs, txvdd = 3.3 v 65 70 75 80 85 90 95 0 10 20 30 40 50 60 sfdr (dbc) f out (mhz) ?6dbfs 0dbfs ?3dbfs 08801-205 figure 8. second harmonic distortion vs. f out o ver digital scale, f dac = 125 mhz, 1 , f ull -s cale c urrent = 2 ma, txvdd = 1.8 v 50 55 60 65 70 75 80 85 90 sfdr (dbc) 0 10 20 30 40 50 60 f out (mhz) 0dbfs ?6dbfs ?3dbfs 08801-206 figure 9. third harmonic di stortion vs. f out o ver digital scale, f dac = 125 mhz, 1 , f ull -s cale c urrent = 2 ma, txvdd = 1.8 v datasheet.in
ad9961/AD9963 rev. 0 | page 14 of 60 60 65 70 75 80 85 90 95 100 0 10 20 30 40 50 60 sfdr (dbc) f out (mhz) 0dbfs ?3dbfs ?6dbfs 08801-207 figure 10 . second harmonic distortion vs. f out o ver digital scale, f dac = 125 mhz, 1 , f ull -s cale c urrent = 2 ma, txvdd = 3.3 v 50 55 60 65 70 75 80 85 90 95 100 0 10 20 30 40 50 60 sfdr (dbc) f out (mhz) 08801-208 ?6 dbfs 0 dbfs ?3 dbfs figure 11 . third harmonic distortion vs. f out o ver digital scale, f dac = 125 mhz, 1 , f ull -s cale c urrent = 2 ma, txvdd = 3.3 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 50 100 150 200 250 power (dbm) frequenc y (mhz) direct clock dl l x25 08801-209 figure 12 . transmit dac output spectrum, f ull -s cale c urrent = 2 ma, txvdd = 3.3 v, f out = 50 mhz, f dac = 125 mhz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 50 100 150 200 250 power (dbm) frequenc y (mhz) direct clock dl l 25 08801-210 figure 13 . transmit dac output spectrum, f ull -s cale c urrent = 2 ma, txvdd = 3.3 v, f out = 10 mhz, f dac = 125 mhz 1.0 0.5 0 ?0.5 ?1.0 0 1024 2048 3584 3072 512 1536 2560 4096 dnl (lsb) samples 08801-211 figure 14 . auxiliary adc dnl 0 1024 2048 3584 3072 512 1536 2560 4096 inl (lsb) samples 1.0 0.5 0 ?0.5 ?1.0 08801-212 figur e 15 . auxiliary adc inl datasheet.in
ad9961/AD9963 rev. 0 | page 15 of 60 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?40 ?35 ?25 ?15 ?5 5 15 25 35 45 55 65 75 85 95 error (c) temper a ture (c) 08801-213 figure 16 . typical die temperature readback error vs. ambient temperature ref ?38.23dbm #avg log 10db/ pavg 10 w1 s2 atten 2db center 21.00mhz #res bw 30khz span 33.84mhz sweep 109.8ms (601pts) rms results carrier power ?25.07dbm/ 3.84000mhz 5.000mhz 10.00mhz 15.00mhz 3.840mhz 3.840mhz 3.840mhz ?73.49 ?72.90 ?73.44 ?98.57 ?97.97 ?98.51 freq offset ref bw dbc lower dbm ?73.85 ?73.11 ?73.56 ?98.92 ?98.19 ?98.63 dbc upper dbm vbw 300khz ext ref dc coupled 08801-214 figure 17 . one - carrier w - cdma aclr performance, if = ~21 mhz 50 55 60 65 70 75 80 85 90 95 100 0 10 20 30 40 50 60 sfdr (dbc) f out (mhz) idac 1.8v cmos second harmonic (dbc) idac 1.8v cmos third harmonic (dbc) 08801-215 figure 18 . ad9961, second and third harmonic distortion vs. f out , f dac = 125 mhz, 1 , digital scale = 0 dbfs, txvdd = 1.8 v 50 55 60 65 70 75 80 85 90 95 100 0 10 20 30 40 50 60 sfdr (dbc) f out (mhz) idac 3.3v cmos second harmonic (dbc) idac 3.3v cmos third harmonic (dbc) 08801-216 figure 19 . ad9961, second and third harmonic distortion vs. f out , f dac = 125 mhz, 1 , digital scale = 0 dbfs, txvdd = 3.3 v 0 10 20 30 40 50 60 70 80 90 100 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr or sfdr (dbc, dbfs) f in (dbm) sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) 08801-217 figure 20 . snr/sfdr vs. analog input level, f in = 10 mhz, f adc = 100 msps 0 10 20 30 40 50 60 70 80 90 100 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr or sfdr (dbc, dbfs) f in (dbm) sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) 08801-218 figure 21 . snr/sfdr vs. analog input level, f in = 70 mhz, f adc = 100 msps datasheet.in
ad9961/AD9963 rev. 0 | page 16 of 60 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 0 512 1024 1536 2048 2560 3072 3584 4096 lsb code in l dn l 08801-219 figure 22 . rx path adc, inl and dnl 135 137 139 141 143 145 147 149 151 153 155 0 10 20 30 40 50 60 70 nsd (?dbm/hz) f out (mhz) idac, 125mhz, 4ma, 0db qdac, 125mhz, 1ma, 0db idac, 125mhz, 2ma, 0db 08801-220 figure 23 . transmit dac noise spectral density vs. f out o ver f ull -s cale c urrent 135 137 139 141 143 145 147 149 151 153 155 0 10 20 30 40 50 60 nsd (?dbm/hz) f out (mhz) idac, 125mhz, 2ma, ?6db idac, 125mhz, 2ma, 0db idac, 125mhz, 2ma, ?3db 08801-221 figure 24 . transmit dac noise spectral density vs. f out o ver digital scale 40 50 60 70 80 90 100 0 10 20 30 40 50 60 imd (db) f out (mhz) idac 35mhz idac 125mhz idac 70mhz 08801-222 figure 25 . intermodulation distortion vs. f out o ver f dac , txvdd = 3.3 v, f ull -s cale c urrent = 2 ma 0 10 20 30 40 50 60 40 50 60 70 80 90 100 imd (db) f out (mhz) qdac, board 3 qdac, board 1 qdac, board 4 08801-223 figure 26 . intermodulation distortion vs. f out , txvdd = 3.3 v, f ull -s cale c urrent = 2 ma, board-to-board v ariation 0 10 20 30 40 50 60 40 50 60 70 80 90 100 imd (db) f out (mhz) qdac ?6db qdac ?3db qdac 0db 08801-224 figure 27 . intermodulation distortion vs. f out o ver digital scale , txvdd = 3.3 v, full - scale c urrent = 2 ma datasheet.in
ad9961/AD9963 rev. 0 | page 17 of 60 60 65 70 75 80 85 90 95 100 80 70 60 50 40 30 20 10 0 snr or sfdr (dbfs) f in (dbm) 08801-225 min pipe snr (dbfs) mid pipe snr (dbfs) max pipe snr (dbfs) min pipe sfdr (dbfs) mid pipe sfdr (dbfs) max pipe sfdr (dbfs) figure 28 . snr/sfdr vs. analog input level over full - scale input r ange, f in = 70 mhz, f adc = 100 msps 70 72 74 76 78 80 0 20 40 60 80 100 120 140 sfdr (db) f in (mhz) 08801-226 figure 29 . AD9963 100 msps single tone ac 60 62 64 66 68 70 0 20 40 60 80 100 120 140 snr (db) f in (mhz) 08801-227 figure 30 . AD9963 1.8 v cmos iadc, 100 msps single tone ac 0 20 40 60 80 100 120 140 thd (dbc) f in (mhz) ?80 ?75 ?70 ?65 ?60 08801-228 figure 31 . AD9963 1.8 v cmos iadc, 100 msps single tone ac ?80 ?78 ?76 ?74 ?72 ?70 0 20 40 60 80 100 120 140 second harmonic (dbc) f in (mhz) 08801-229 figure 32 . AD9963 1.8 v cmos iadc, 100 msps single tone ac ?90 ?85 ?80 ?75 ?70 ?65 0 20 40 60 80 100 120 140 third harmonic (dbc) f in (mhz) 08801-230 figure 33 . AD9963 1.8 v cmos iadc, 100 msps single tone ac datasheet.in
ad9961/AD9963 rev. 0 | page 18 of 60 terminology linearity error (integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. differential nonlinearity (dnl) dnl is the measure of the va riation in analog value, normal ized to full scale, associated with a 1 lsb change in digital input code . monotonicity a d ac is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called offset error. for txin , 0 ma output is expected when the inputs are all 0s. for txip , 0 ma output is expected when all inputs are set to 1 . gain error the differen ce between the actual and ideal output span. the actual span is determined by the difference between the outp ut when all inputs are set to 1 and the output when all inputs are set to 0. output compliance range the range of allowable voltage at the output of a current - output dac. operation beyond the maximum co mpliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. temperature drift temperature drift is specified as the ma ximum change from the ambient ( 25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in parts per million of full - scale range (fsr) per degree celsius (c) . for reference drift, the drift is reported in p arts per ppm/c . power supply rejection the maximum change in the full - scale output as the supplies are varied from minimum to maximum specified voltages. settling time the time requ i red for the output to reach and remain within a specified error band a round its final value, measured from the start of the output transition. spurious free dynamic range (sfdr) the difference, in decibels , between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. total harmonic distortion (thd) thd is the ratio of the rms sum of the first si x harmonic com - ponents to the rms value of the measured fundamental. it is expressed as a percentage or in decibels. signal -to - noise ratio (snr ) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels . adjacent channel leakage ratio (aclr) the ratio in dbc between the measured power within a channel relative to its adjacent channel. complex image rejection in a traditional two - part up conversion, two images are created around the second if frequency. these images have the effect of wasting transmitter power and system bandwidth. by placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second if can be rejected. datasheet.in
ad9961/AD9963 rev. 0 | page 19 of 60 theory of operation the ad9961/ ad99 63 are targeted to cover the mixed -signal front - end needs of multiple wireless communications systems. th ey feature a receive path that consists of dual 10 - /12 - bit receive adcs and a transmit path that consists of dual 10- /12 - bit transmit dacs (txdac). the ad9961/AD9963 integrate additional functionality typically required in most systems, such as power scal ability, tx gain control, and clock multiplication circuitry. the ad9961/AD9963 minimize both size and power consumption to address the needs of a range of applications from the low power portable market to the high performance femto base station market. t he part is provided in a 72 - lead lead frame chip scale package (lfcsp) that has a footprint of only 10 mm 10 mm. power consumption can be optimized to suit the particular application by incorporating power - down controls, low power adc modes , and txdac po wer scaling. i n full duplex mode , the ad9961/AD9963 use two 12 - bit buses, along with qualifying clock signals, to transfer rx path data and tx path data. these two buses support either single data rate or double data rate data transfers. the data bus, alo ng with many other device options, is configurable through the serial port by writing internal registers. the devi ce can also be used in a single- port, half - duplex configuration. datasheet.in
ad9961/AD9963 rev. 0 | page 20 of 60 serial control port the ad9961/AD9963 serial control port s are a flexible, sy nchronous, serial communications port that allows an easy interface with many industry - standard microcontrollers and microprocessors. the ad9961/AD9963 serial control port s are compatible with most synchronous transfer formats, including both the motorola spi and intel? ssr? protocols. the serial control port allows read/write access to all registers that configure the ad9961/AD9963. single or multiple byte transfers are supported, as well as msb first or lsb first transfer formats. serial control port pin descriptions the serial control port has three pins, sclk, sdio , and cs ? sclk (serial clock) is the input clock used to register serial control port reads and writes. write data bits are registered on the rising edge of this clock, and r ead data bits are registered on the falling edge. this pin is internally pulled do wn by a 30 k ? resistor to ground. : ? sdio (serial data input/output) functions as both the input and output data pin. ? cs (chip select bar) is an active low control that gates the read and write cycles. when general operation of serial control port cs is high, sdio is in a high impedance state and sclk is disabled. this pin is internally pulled up by a 30 k ? resistor to drvdd . the falling edge of cs instruction header , in conjunction with the rising edge of sclk , determines the start of a communication cycle. there are two parts to a communication cycle with the ad9961/ AD9963. the first part writes a 16 - bit instruction word into the ad9961/AD9963, coincident with the first 16 sclk rising edges. the instruction word provides the ad9961/AD9963 serial control port s with information regarding the data transfer, which is the second part of the communication cycle. the instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. the msb of the instruction word is r/ w for a write, the instruction word is followed by the number of bytes of data indicated by bit n1 to bit n0 (see , which indicates whether the serial port transfer is a read or a write. the next two bit s, n1:n0, indicate the length of the transfer in bytes. the fin al 13 bits are the address (a12 to a0) at which to begin the read or write operation. table 10 ). table 10 . byte transfer count n1 n0 bytes to transfer 0 0 1 0 1 2 1 0 3 1 1 streaming mode a 12 to a0 select the address within the register map that is written to or read from during the data transfer portion of the communications cycle. for multibyte transfers, the address is the starting byte address. only address bits [a7:a0] are needed to cover the range of the 0xff registers used by the ad9961/AD9963. address bits [a12:a8] must al ways be 0. write transfer if the instruction header indicates a write operation, the bytes of data written onto the sdio line are loaded into the serial control port buffer of the ad9961/AD9963. data bits are registered on the rising edge of sclk. the len gth of the transfer (1 byte , 2 byte , 3 bytes , or streaming mode) is indicated by two bits (n1:n0) in the instruction byte. during a write, streaming mode does not skip over unused or reserved registers; therefore, the user must know what bit pattern to wri te to the reserved registers to preserve proper operation of the part. it does not matter what data is written to unused registers. read transfer if the instruction word is for a read operation, the next n 8 sclk cycles clock out the data from the addres s specified in the instruction word, where n is 1 to 3 as determined by n1:n0. if n = 4, the read operation is in streaming mode, and continue s until cs msb/lsb first transfers is raised. streaming mode does not skip over reserved or unused registers. the readb ac k data is valid on the falling edge of sclk. the ad9961/AD9963 instruction word and byte data format s can be selected to be msb first or lsb first. the default for the ad9961/AD9963 is msb first. when msb first mode is active, th e instruction and data bytes must be written from msb to lsb. multibyte data transfers in msb first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes must follow in order from the high address to the low address. in msb first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle. when lsb first is active, the instruction and data bytes must be written from lsb to msb. multibyte data transfers in lsb first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. the internal byte address generator of the serial control port increment s for each byte of the multibyte transfer cycle. datasheet.in
ad9961/AD9963 rev. 0 | page 21 of 60 when lsb first is set by register 0x00 , bit 2 and register 0x00 , bit 6 , it takes effect immediately. in multibyte transfers, subsequent bytes reflect any changes in the serial port configuration. to avoid problems reconfiguring the serial port operation, any data written to 0x00 must be mirrored (the eight bits should read the same, forward or backward). mirroring the data makes it irrelevant whether lsb first or msb first is in effect. as an example of this mirroring, the default setting for r egister 0x00 is 00011000. ending transfers when the transfer is 1, 2, or 3 bytes, the data transfer ends after the required number of clock cycles have been received. cs can be raised after each seque nce of eight bits to stall the bus (e xcept after the last byte, where it ends the cycle). when the bus is stalled, the serial transfer resumes when cs is lowered. raising cs on a non byte boundary resets the serial contr ol port. the ad9961/AD9963 serial control port register address es decrement from the register address just written toward 0x00 for multibyte i/o operations if the msb first mode is active (default). if the lsb first mode is active, the register address of the serial control port increments from the address just written toward 0xff for multibyte i/o operations. streaming mode transfers always terminate when table 11 . streaming mode (no addresses are skipped) cs is raised. streaming mode transfers also terminate whenever the address reaches 0 xff. note that unused addresses are not skipped during multibyte i/o operations. to avoid unpredictable device behavior, do not write to reserved registers. write mode address dire ction stop sequence lsb first increment 0xfd, 0xfe, 0xff, stop msb first decrement 0x01, 0x00, 0xff, stop s ub serial interface c ommunications the AD9963/ad9961 ha ve two registers that require a different communication sequence. these registers are 0x0f and 0x10. the write sequence for these two registers requires a write to r egister 0x05, a write to the r egister (0x0f or 0x10), and then a write to r egister 0xff. the write takes effect when the write to r egister 0xff is completed. for example, to enable t he rxcml pin output buffer, the register write sequence is : 1. write 0x03 into register 0x05. this addresses both of the rx adcs. 2. write 0x02 into register 0x0f. this sets the rxcml enable bit. 3. write 0x01 into register 0xff. this updates the internal register, which activates the rxcml buffer. 4. write 0x00 into register 0x05. this returns the spi to the normal addressing mode. an example of updating r egister 0x10 is given in the adc digital offset adjustment section. table 12 . serial control port, 16 - bit instruction word, msb first msb lsb i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/ w n1 n0 0 0 0 0 0 a7 a6 a5 a4 a3 a2 a1 a0 cs sclk don?t care sdio a12n0n1r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don?t care don?t care don?t care 16-bit instruction header register (n) data register (n ? 1) data 08801-038 figure 34 . serial control port access ? msb first, 16 - bit instruction, 2- byte data t s don?t care don?t care n1 n0 a12 a11 a10 a9 a8 a7 a6 a5 d4 d3 d2 d1 d0 don?t care don?t care r/w t ds t dh t high t low t clk t c cs sclk sdio 08801-040 figure 35 . serial control port write ? msb first, 16 - bit instruction, timing measurements datasheet.in
ad9961/AD9963 rev. 0 | page 22 of 60 data bit n ? 1 data bit n cs sclk sdio sdo t dv 08801-041 figure 36 . timing diagram for serial control port register read cs sclk don?t care don?t care 16-bit instruction header register (n) data register (n + 1) data sdio don?t care don?t care a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d1d0r/wn1n0 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 08801-042 figure 37 . serial control port access lsb first, 16 - bit instruction, two bytes data cs sclk sdio t high t low t clk t s t ds t dh t c bit n bit n + 1 08801-043 figure 38 . serial control port timing write table 13 . serial cont rol port timing parameter timing (min, n s) description t ds 5 .0 setup time between data and rising edge of sclk . t dh 5.0 hold time between data and rising edge of sclk . t clk 20.0 period of the clock . t s 5 .0 setup time between cs fallin g edge and sclk rising edge (start of communication cycle) . t c 2 setup time between sclk rising edge and cs rising edge (end of communication cycle) . t hi gh 10 minimum period that sclk should be in a logic high state . t lo w 10 minimum pe riod that sclk should be in a logic low state . t dv 5.0 sclk to valid sdio and sdo (see figure 36 ). datasheet.in
ad9961/AD9963 rev. 0 | page 23 of 60 configuration regist ers table 14. configuration register map addr default bit 7 bit 6 bi t 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 0x18 sdio lsb first r eset 1 1 r eset lsb first sdio 0x05 0x00 unused addrq addri 0x0f 0x00 rxcml 0x10 0x00 unused adc_offset[5:0] 0x30 0x3f unused dec_bp int1_bp int0_bp srrc_bp txclk_en rxclk_en 0x31 0xa7 tx _sdr txcko_inv txclk_md[1:0] txcki_inv txiq_hilo tx_ifirst tx_bnry 0x32 0xa7 rx_sdr unused rxclk_md[1:0] rxclk_inv rxiq_hilo rx_ifirst rx_bnry 0x33 varies unused fifo_init a ligned align_ack align_req fifo_offset[2:0] 0x34 varies fifo_lvl[7:0] 0x35 0x10 unused srrc_scale[4:0] 0x36 0x08 unused int0_scale[4:0] 0x37 0x10 unused int1_scale[4:0] 0x38 0x06 unused dec_scale[4:0] 0x39 0x00 rxdllrst txdllrst unused rxdll_lkd txdll_lkd rxdbl_sel txdbl_sel 0x3a 0x51 tx_unlock[1:0] tx_lock[1:0] tx_dlyofs[1:0] t x_hyst[1:0] 0x3b 0x51 rx_unlock[1:0] rx_lock[1:0] rx_dlyofs[1:0] rx_hyst[1:0] 0x3c 0xf0 dbl_tapdly[7:0] 0x3d 0x00 unused rx_invq rx_invi tx_invq tx_invi 0x3e 0x09 unused tx_dblpw[2:0] rx_dblpw[2:0] 0x3f 0x07 unused rx_clk rx_ bus singlerx txclk_md hd_b usctl hd_clkmd f ull _d uplex 0x40 0x01 dac12b_en dac12a_en dac12b_ t op dac12a_ t op unused aux dac_ r ef dac_ u pdate 0x41 0x00 dac12a[11:4] 0x42 0x00 unused dac12a[3:0] 0x43 0x00 dac12b[11:4] 0x44 0x00 unused dac12b[3:0] 0x45 0x00 dac10 b _en unused dac10 b_top [2:0] dac10 b _rng[1:0] 0x46 0x00 dac10 b [9:2] 0x47 0x00 unused dac10 b [1:0] 0x48 0x00 dac10 a _en unused dac10 a_top [2:0] dac10 a _rng[1:0] 0x49 0x00 dac10 a [9:2] 0x4a 0x00 unused dac10 a [1:0] 0x50 0x00 unused tx_pttrn tx_insel tx_cont tx_start tx_bisten 0x5 1 0x00 unused rx_pttrn rx_insel rx_cont rx_start rx_bisten 0x52 0x93 txi_chk[15:8] 0x53 0x34 txi_chk[7:0] 0x54 0x5f txq_chk[15:8] 0x55 0x36 txq_chk[7:0] 0x5c 0x0 8 c hip id[7:0] 0x60 0x00 dll_en txdac_pd txi_s leep txq_s leep clk_pd rxadc_pd rxq_s leep rx i_s leep 0x61 0x00 unused dll_ ldo _ pd dllbias_pd clk_ ldo _ pd rx_ ldo _ pd rxf_ ldo _ pd aux adc_pd aux _ref_pd 0x62 0xf8 dll_ldo _ stat clk_ ldo _ stat rx_ ldo _ stat rxf_ ldo _ stat dig_ ldo _ stat unused unused rset_sel 0x63 0x00 t rxd_drv t rxiq_drv t rxclk_drv txclk_drv 0 x66 0x28 txi_dclk txq_dclk unused rxi_dclk rxq_dclk dcs_bp adcdiv[1:0] 0x68 0x00 unused igain1[5:0] 0x69 0x00 unused igain2[5:0] 0x6a 0x00 unused irset[5:0] 0x6b 0x00 unused qgain1[5:0] 0x6c 0x00 unused qgain2[5:0] 0x6d 0x00 unused qrset[5:0] 0x6e 0 x40 unused refio_adj[5:0] datasheet.in
ad9961/AD9963 rev. 0 | page 24 of 60 addr default bit 7 bit 6 bi t 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x71 0x00 adcclksel dacclksel unused dll_ref_en n[3:0] 0x72 0x01 dll_locked dlldiv m[4:0] 0x75 0x00 0 dll_resb 0 0x77 0x00 conv_time[1:0] unused auxadc_ch[2:0] 0x78 varies auxadc[11:4] 0x79 varies auxadc[3:0] c onv_compl chan _sel[2:0] 0x7a 0x00 a ux adc_en a ux adc_resb unused auxdiv[2:0] 0x7b 0x00 tmpsns_en unused auxref_adj[2:0] unused 0x7d 0x00 unused rx_fsadj[4:0] 0x7e 0x00 unused rxtrim_en rxtrim_fine auxcml_en 0 rx_dc 0x7f 0x00 rxi_trim[9:2] 0x80 0x00 unused rxi_trim[1 :0] gaincal_ eni 0x81 0x00 rxq_trim[9:2] 0x82 0x00 unused rxq_trim[1:0] gaincal_ enq 0xff 0x00 unused u pdate configuration regist er bit descriptions table 15. register name register address bit (s) parameter function serial po rt config 0x00 7 , 0 sdio 0: use sdio pin as input data only . 1: use sdio as both input and output data . 6 , 1 lsb_ first 0: first bit of serial data is msb of data byte . 1: first bit of serial data is lsb of data byte . 5 , 2 reset a transition from 0 to 1 on this bit resets the device. all registers but r egister 0x00 revert to their default values. adc address 0x05 1:0 addrq, addri bits are set to determine which device on chip receives adc specific write commands. adc specific write commends include writes to r egisters 0x0f and register 0x10. these w rites also require a rising end on the u pdate bit ( r egister 0xff, b it 0). 00: n o adcs are addressed. 01: i adc is addressed. 10: q adc is addressed 11: b oth i and q adcs are ad dressed. cm b uffer enable 0x0f 1 rxcml enable control for the rxcml output buffer. note that updating this bit also requires writing to register 0x05 and register 0xff as described in the sub serial interface communications section. 0: rxcml pin is high impedance. 1: rxcml pin is a low impedance 1.4 v output. adc offset 0x10 5:0 adc_o ffset[5:0] adds a dc offset to the adc output of whichever adc is addressed by r egister 0x05. the offset applied is as follows: 011111: offset = +31 lsbs 000001: offset = +1 lsb 000000: offset = 0 lsb 111111: offset = ? 1 lsb 100000: offset = ?32 lsbs digital filters 0x30 7:6 unused 5 dec_bp 1: bypass 2 decimator in rx path (d0) . 4 int1_bp 1: bypass 2 h alf -b and i nterpolation f ilter 1 ( int1 ). 3 int0_bp 1: bypass 2 h alf -b and i nterpolation f ilter 0 ( int0 ). datasheet.in
ad9961/AD9963 rev. 0 | page 25 of 60 register name register address bit (s) parameter function 2 srrc_bp 1: bypass 2 srrc interpolation filter (srrc) . the filter chain is srrc int0 int1 . if srrc filter is enabled, t he other two filters are enabled too. 1 txclk_en 1: enables data clocks for transmit path . 0 rxclk_en 1: enables data clocks for receive path . tx data interface 0x31 7 tx_sdr 0: c hooses ddr clocking mode. tx d ata is driven out on both edges of the t xclk signal. 1: c hooses b us r ate clocking mode. tx d ata is driven out on one edge of the txclk signal. 6 txcko_inv this signal inverts the phase of the transmit path output clock signal. 0: t ransmit path data transitions on the positive edge of the txclk signal. 1 : t ransmit path data transitions on the positive edge of the txclk signal. 5:4 txclk_md [ 1:0 ] controls the mode of the txclk pin. the txclk pin can be configured as an input or an output. when configured as an output, it can ha ve two possible sources, the internal txclk signal or the dll output signal. 00: d isabled . 01: t he txclk pin is configured as an input. 10: t he txclk pin is configured as an output. the sou r ce signal is the transmit path clock signal. 1 1: t he txclk pin is configured as an output. the sou r ce signal is the dll ou t put signal. note that the txclk signal may appear on either the txclk pin or the trxclk pin, depending on the mode of the device. in half - duplex 1 - clock mode, this signal is present on the trxclk pin when tx is active. in half - duplex 2 - clock mode and full - duplex m ode, this signal is present on the txclk pin. 3 txcki_inv selects which edge of the txclk signal samples the transmit path data. 0: txpclk negative edge latch es transmit path data . 1 : txpclk positive edge latches transmit path data . 2 txiq_hilo data app ears on the txd bus sequentially but is loaded into the transmit path in pairs. txiq_hilo selects how the txiq signal marks each data pair. 0: e ach data pair is marked by txiq being low then high. 1: e ach data pair is marked by txiq being high then low. 1 tx_ifirst this bit sets the data pairing order of the i and q samples on transmit path. 0 : s elects that q is first, followed by i. 1: s elects that i is first , followed by q. 0 tx_bn ry this bit selects the data format of the transmit path data. 0: selects two s complement. 1: s elects straight binary . rx data interface 0x32 7 rx_sdr 0: c hooses ddr clocking mode. rx data is driven out on both edges of the trxclk signal. 1: c hooses b us r ate clocking mode. r x d ata is driven out on one edge of the trxclk signal. 6 unused 5:4 rxclk_md[1:0] this sets the way the internal rxclk signal in the chip is driven. 00: d isabled . 01: d isabled . 1 0: rxclk is driven by internal r x path clock. datasheet.in
ad9961/AD9963 rev. 0 | page 26 of 60 register name register address bit (s) parameter function 11: rxclk is driven by the dll output. note that the rxclk signal is present on the trxclk pin with one exception. in half - duplex 1 - clock mode, the rxclk signal is pr esent on the trxclk p in when r x is active, but the t xclk signal appears on the trxclk pin when tx is active. 3 rxc lk_inv 0: uses trxclkio neg ative edge to drive out rxdata. 1: uses trxclkio pos itive edge to drive out rxdata. 2 rxiq_hilo data app ears on the rxd bus sequentially but is sampled in the r x path in pairs. rxiq_hilo selects how the rxiq signal marks each data pair. 0: e ach data pair is marked by rxiq being low then high. 1: e ach data pair is marked by rxiq being high then low. 1 rx _ifirst the rx path i and q adcs sample simultaneously producing a pair of samples. because the rxd bus is shared, the sampled i and q data appears on the trxd bus sequentially. this bit determines the order of the paired samples. 0: q appears firs t on rx path . 1: i appears first on rx path . 0 rx_bn ry 0: two s complement on tx path. 1: straight binary on tx path . fifo alignment 0x33 7 unused 6 fifo_init 1: fifo read and write pointers are aligned after chip reset . 5 a ligned 1: fi fo read and write pointers aligned after f rame input driven fifo reset . 4 align_ack 1: fifo read and write pointers aligned after s erial p ort driven fifo reset. 3 align_req 1: r equest fifo read and write pointers alignment via s erial p ort. 2:0 fif o_off set[ 2:0 ] sets the fifo read and write pointer phase offset following fifo reset. normally this should be set to 4 to set the fiffo to half full. 000 = 0. 001 = 1. 111 = 7. fifo status 0x34 7:0 fifo_lvl[7:0] indicator of the amount of valid data in the fifo. each one indicates a latched input sample in the fifo. ideally, the eigh t deep fifo should be half full, indicating four latched input samples. the indicator is a thermometer code that can wrap around from lsb to msb. some exa mples follow: 00011110: i ndicates that fifo is half full. the read pointer is 1 and the write pointer is 5. 10000111: i ndicates the fifo is half full. the read pointer is 3 and the write pointer is 7. 00100000: i ndicates the fifo has only on e latched sample and is nearly empty. 01111111: i ndicates the fifo has seven latched samples and is nearly over flowing. tx scale p 0x35 7:5 unused 4:0 srrc_scale[4:0] value of 1.4 m ultiplier applied to both i and q channels just after the srrc f ilter. 00000: m ultipl y by 0.0 . 00001: m ultipl y by 0.0625 . 11111 : m ultipl y by 1.9375 . tx scale 0 0x36 7:5 unused 4:0 int0_scale[4:0] value of 1.4 m ultiplier applied to both i and q channels just after interpolation filter 0. datasheet.in
ad9961/AD9963 rev. 0 | page 27 of 60 register name register address bit (s) parameter function 00000 : m ultip ly by 0.0 . 00001: m ultipl y by 0.0625 . tx scale 1 0x37 7:5 unused 1111 1: m ultipl y by 1.9375 . 4:0 int1_scale[4:0] value of 1.4 m ultiplier applied to both i and q channels just after interpolation filter 1. 00000: m ulti pl y by 0.0 . 00001: m ultipl y by 0.0625 . 11111 : m ultipl y by 1.9375 . rx scale 0x38 7:5 unused 4:0 dec_scale[4:0] value of 3.2 m ultiplier applied to both i and q channels just after the d ecimation f ilter. the value of the gain applied is equal to dec_scale/4. 00000: m ultipl y by 0.0 . 00001: m ultipl y by 0.25 . 11111: m ultipl y by 7.75 . clock doubler config 0x39 7 rxdllrst 1: r esets the rx signal path clock doubler . 6 txdllrst 1: r esets the tx signal path clock doubler . 5:4 unus ed 3 rxdll_lkd the r x c lock doubler is locked. 2 txdll_lkd the t x c lock doubler is locked. 1 rxdbl _sel 0: s elects fixed pulse width clock doubler . 1: s elects fixed duty cycle clock doubler . see table 22 for con figuration recommendations. 0 txdbl _sel 0: s elects fixed pulse width clock doubler . 1: s elects fixed duty cycle clock doubler . see table 22 for configuration recommendations. tx clock doubler config 0x3a 7:4 tx_unloc k[1:0] sets the number of clock cycles for the unlock indicator. set to 01. 3 tx_lock[1:0] sets the number of clock cycles for the lock indicator. set to 01. 2 tx_dlyofs[1:0] sets delay line offset of clock doubler. set to 01 . 1 tx_hyst[1:0] sets delay line hysteresis of clock doubler. set to 01. rx clock doubler config 0x3b 7:4 rx_unlock[1:0] sets the number of clock cycles for the unlock indicator. set to 01 . 3 rx_lock[1:0] sets the number of clock cycles for the lock indicator. set to 01 . 2 rx_dlyofs[1:0] sets delay line offset of clock doubler. set to 01 . 1 rx_hyst[1:0] sets delay line hysteresis of clock doubler. set to 01 . clock doubler config 0x3c 7:0 dbl_tapdly[7:0] sets the initial tap delay of the r x and t x clock doublers. set t o 0x02. data spectral inversion 0x3d 7:4 unused 3 rx_inv q 1: multipl y rxdata from qadc by ?1. 2 rx_inv i 1: multipl y rxdata from iadc by ?1. 1 tx_inv q 1: multipl y txdata for qdac by ?1. 0 tx_inv i 1: multipl y txdata for idac by ?1. clock doubler pulse width 0x3e 7:6 unused 5:3 tx _ dblpw[2:0] sets the pulse width of the t x clock doubl er. see table 22 for details. 2:0 rx _ dblpw[2:0] sets the pulse width of the r x clock doubler. see table 22 for details. datasheet.in
ad9961/AD9963 rev. 0 | page 28 of 60 register name register address bit (s) parameter function rx data interface 0x3f 7 unused 6 rx_clk 0: when singlerx is active, use q s ide clock. 1: when singlerx is active, use i side clock. 5 rx_bus 0: when singlerx is active, use the q adc. 1: when singlerx is active, use the i adc. 4 singlerx 0: use both rx paths. 1: use only one rx path. 3 txclk_md this bit co ntrols the operation of the txclk pin when the chip is configured in half - duplex 1 - clock mode. this bit is otherwise ignored. 0: the txclk pin is set to a high impedance output. 1: the dll clock output is driven onto the txclk pin. 2 hd_busctl 0: selects spi mode to control bus direction in half - duplex mode . 1: selects pin mode to control bus direction in half - duplex mode . spi bit to set tx or rx is register 0x30, bit 0. register 0x30, bit 1 is ignored in this case. 1 hd_clkmd 0: s elects 1 - clock submode if in half - duplex mode. 1: selects 2 - clock submode if in half - duplex mode. 0 full_duplex 0: configures the digital interface for half - duplex mode (covers both 1 - clock and 2 - clock submodes). 1: configures the digital inte rface for full - duplex mode. dac12 config 0x40 7 dac12b_en 0: powers down dac12b. 1: enables dac12b. 6 dac12a_en 0: powers down dac12a. 1: enables dac12a. 5 dac12b_top 0: sets dac12b range to 3.3 v auxdacr ef . 1: sets dac12b range to 1 .8 v auxdacr ef . 4 dac12a_top 0: sets dac12a range to 3.3 v auxacr ef . 1: sets dac12a range to 1.8 v auxdacr ef . 3:2 unused 1 auxdac_ref selects where the voltage reference for all of the auxiliary dacs is derived. 0: resistive divider from aux33v. v auxdacref = v aux33v /3.3. 1: selects the 1.0 v bandgap voltage. v auxdacr ef = 1.0 v. 0 dac_update this bit determines which of the two data words updates all four of the auxiliary dacs. 0: update dacs after lsb write. 1: upda te dacs after msb write. dac12a msbs 0x41 7:0 dac12a[11:4] dac12a voltage control word (upper eight bits). dac12a lsbs 0x42 7:4 unused 3:0 dac12a[3:0] dac12a voltage control word (lower four bits). dac12b msbs 0x43 7:0 dac12b[11:4] dac12b voltage co ntrol word (upper eight bits). dac12b lsbs 0x44 7:4 unused 3:0 dac12b[3:0] dac12b voltage control word (lower four bits). dac10b config 0x45 7 dac10b_en 0: powers down dac10b . 1: enables dac10b . 6:5 unused 4:2 dac10b_top[2:0] sets the dac output voltage at the top range as follows: 000: 1.0 v. 001: 1.5 v. datasheet.in
ad9961/AD9963 rev. 0 | page 29 of 60 register name register address bit (s) parameter function 010: 2.0 v. 011: 2.5 v. 100: 3.0 v. 1:0 dac10b_rng[1:0] the total range of the dac extends from top - of - range, to top - of - range minus the span. the span is set a s: 00: 2.0 v. 01: 1.5 v. 10: 1.0 v. 11: 0.5 v. dac10bmsbs 0x46 7:0 dac10b[9:2] dac10b voltage control word ( eight most significant bits). dac10blsbs 0x47 7:2 unused 1:0 dac10 b [1:0] dac10bvoltage control word (two least significant bits). dac10a config 0x48 7 dac10a_en 0: powers down dac10a . 1: enables dac10a . 6:5 unused 4:2 dac10a_t o p[2:0] sets the dac output voltage at the top range as follows: 000: 1.0 v. 001: 1.5 v. 010: 2.0 v. 011: 2.5 v. 1 00: 3.0 v. 1:0 dac10a_rng[1:0] the total range of th e dac extends from top - of - range to top - of - range minus the span. the span is set as: 00: 2.0 v. 01: 1.5 v. 10: 1.0 v. 11: 0.5 v. dac10a msbs 0x49 7:0 dac10a[9:2] dac10a voltage cont rol word ( eight most significant bits). dac10a lsbs 0x4a 7:2 unused 1:0 dac10a[1:0] dac10a voltage control word ( two least s ignificant bits). tx bist control 0x50 7:5 unused unused 4 tx_pttrn chooses the pattern type for the bist sequence. 0: s elects checker board pattern (0xa5a, 0x5a5, 0xa5a, ). 1: selects prn output. 3 tx_insel 0: selects pattern input from internal pattern generator. 1: selects pattern from the external pins of the tx port. 2 tx_cont 0: runs the bist for 512 cycles. 1: runs the bist continuously. 1 t x_start 0: keep the bist engine in an idle state. 1: start the bist sequence. 0 tx_bisten 0: disable the bist engine. 1: enable the bist engine. rx bist control 0x51 7:5 unused 4 rx_pttrn chooses the pattern type for the bist sequence. 0: selects checker board pattern (0xa5a, 0x5a5, 0xa5a, ). 1: selects prn output. 3 rx_insel 0: selects pattern input from internal pattern generator. 1: selects pattern from the external pi ns of the rx path. 2 rx_cont 0: runs the bist for 512 cycles. 1: runs the bist continuously. datasheet.in
ad9961/AD9963 rev. 0 | page 30 of 60 register name register address bit (s) parameter function 1 rx_start 0: keep the bist engine in an idle state. 1: start the bist sequence. 0 rx_bisten 0: disable the bist engine. 1: enable the bist engine. txi check msb 0x52 7:0 txi_chk[15:8] msb of the bist signature value for the i side transmit path. txi check lsb 0x53 7:0 txi_chk[7:0] lsb of the bist signature value for the i side transmit path. txq check msb 0x54 7:0 txq_chk[15:8] msb of the bist signature value for the q side transmit path. txq check lsb 0x55 7:0 txq_chk[7:0] lsb of the bist signature value for the q side transmit path. version 0x5c 7:0 c hip id[7:0] indicates device hardware revision number. should read back as 0x08. powe r down 0 0x60 7 dll_en 0: powers down dll block. 1: enables dll block. 6 txdac_pd 1: powers down the bandgap reference voltage common to both transmit dacs and all of the auxiliary dacs. 5 txi_sleep 1: turns off idac output current. 4 txq_sle ep 1: turns off qdac output current. 3 clk_pd 1: turns off clock receiver. this disables all clocks on the chip except for the serial port clock. 2 rxadc_pd 1: powers down main adc clock and the bandgap reference voltage common to both receive adc s. 1 rxq_sleep 1: p owers down the q adc core. 0 rxi_sleep 1: p owers down the i adc core. power down 1 0x61 7 unused 6 dll_ldo_pd 1: powers down ldo that supplies the dll18v voltage rail. 5 dllbias_pd 1: powers down bias sub - block inside dll bloc k. 4 clk_ldo_pd 1: powers down ldo that supplies the clk18v voltage rail. 3 rx_ldo_pd 1: powers down ldo that supplies the rx18v voltage rail. 2 rxf_ldo_pd 1: powers down ldo that supplies the rx18vf voltage rail. 1 auxadc_pd 1: powers down aux adc block. 0 aux_ref_pd 1: powers down the auxiliary adc voltage reference, allowing an external reference to be used. ldo status 0x62 7 dll_ldo_stat 1: ldo to dll block is on (read only). 6 clk_ldo_stat 1: ldo to clock block is on (read only). 5 rx_ldo_stat 1: ldo to adc blocks is on (read only). 4 rxf_ldo_stat 1: ldo to flash section of adc is on (read only). 3 dig_ldo_stat 1: ldo to digital core is on (read only). 2 unused 1 unused 0 rset_sel 0: selects internal 10 k? to generate 1 v reference. 1: selects external rset to generate voltage reference. output drive 0x63 7:6 t rxd_drv controls the drive strength of the t rxd[11:0] pins. 00: 4 ma output drive. 01: 8 ma output drive. 10: 12 ma output drive. 11: not valid. 5:4 t rxiq_drv controls the drive strength of the t rxiq pin. 00: 4 ma output drive. 01: 8 ma output drive. 10: 12 ma output drive. 11: not valid. datasheet.in
ad9961/AD9963 rev. 0 | page 31 of 60 register name register address bit (s) parameter function 3:2 t rxclk_drv controls the drive strength of the t rxclk pin. 00: 4 ma output drive. 01: 8 ma output drive. 10: 12 ma output drive. 11: not valid. 1:0 txclk_drv controls the drive strength of the txclk pin. 00: 4 ma output drive. 01: 8 ma output drive. 10: 12 ma output drive. 11: not v alid. clock mode 0x66 7 txi_dclk 1: disables internal clock to i dac. 6 txq_dclk 1: disables internal clock to q dac. 5 unused 4 rxi_dclk 1: disables internal clock to i adc. 3 rxq_dclk 1: disables internal clock to q adc. 2 dcs_bp 1: disa bles duty cycle stabilizer block. 1:0 adcdiv[1:0] 00: selects divide by 1. bypasses internal divider block for rxclk. 01: selects divide by 1. bypasses internal divider block for rxclk. 10: selects divide by 2. 11: selects divide by 4. i dac gain ctrl 0 0x68 7:6 unused 5:0 igain1 [ 5:0 ] linear in db adjustment of the full - scale current of idac . provides an adjustment range of approximately 6 db in 0.25 db steps. see figure 57 for details. i dac gain ctrl 1 0 x69 7:6 unused 5:0 igain2 [ 5:0 ] linear adjustment of the full - scale current of i dac . provides an adjustment range of approximately 2.5% in 0.08% steps. see figure 55 for details. i dac gain ctrl 2 0x6a 7:6 unused 5:0 irse t[ 5:0 ] linear adjustment of the full - scale current of i dac . provides an adjustment range of approximately 20% in 0.625% steps. see figure 55 for details. q dac gain ctrl 0 0x6b 7:6 unused 5:0 qgain1 [ 5:0 ] linear in db adjust ment of the full - scale current of q dac . provides an adjustment range of approximately 6 db in 0.25 db steps. see figure 56 for details. q dac gain ctrl 1 0x6c 7:6 unused 5:0 qgain2 [ 5:0 ] linear adjustment of the full - scale cu rrent of q dac . provides an adjustment range of approximately 2.5% in 0.08% steps. see figure 57 for details. q dac gain ctrl 2 0x6d 7:6 unused 5:0 qrset [ 5:0 ] linear adjustment of the full - scale current of q dac . provides an adjustment range of approximately 20% in 0.625% steps. see figure 55 for details. refio adjust 0x6e 7:6 unused 5:0 refio_adj [ 5:0 ] adjusts the on - chip reference voltage and output at refio . the transmit dac full - scale current s and the auxiliary dac full - scale voltages are proportional to the refio voltage. the approximate refio output voltage by code is: 000000: v ref = 1.0 v. 000001: v ref = 1.00625 v. 011111: v ref = 1.19375 v. datasheet.in
ad9961/AD9963 rev. 0 | page 32 of 60 register name register address bit (s) parameter function 100000: v ref = 0.8 v. 100001: v ref = 0.80625 v. 111111 : v ref = 0.99375 v. dll control 0 0x71 7 adcclk sel 1: selects dll output as the adc sampling clock. 0: selects external clock as the adc sampling clock. 6 dacclk sel 1: selects dll output as the dac sampling clock. 0: selects external clock as the dac sampling clock. 5 unused 4 dll_ref_en 1: e nables the input reference clock to the dll. 3:0 n[3:0] sets dll divide ratio (1 to 8) at the output of the dll. 0000: n ot v alid . 0001: 1. 0010: 2 . 0110: 6. 0111: not valid. 1000: 8 . 1001: not v alid . 1111: not v alid . dll control 1 0x72 7 dll_locked 1: dll has locked to reference clock (read only) . 6 :5 dlldiv [1:0] 00 : dll output is directly dr iven out. divider is bypassed. 0 1: dll output is directly driven out. divider is bypassed. 10: dll output is divided by 2. 11: dll output is divided by 4. 4:0 m[ 4:0 ] sets dll multiplication factor (1 to 32) . 00000: 1 . 00001: 2 . 11111: 32 . dll control 2 0x75 7 :4 0 set these bits to 0. 3 dll_resb reset dll . the dll must be reset by a low to high transition on this bit each time the dll configuration is changed or the reference frequency is changed. 2 :0 0 set thes e bits to 0. aux adc config 0x77 7:6 conv_time[ 1:0 ] sets the number of auxadcclk cycles required to perform a conversion. and conversion start 00: 20 auxadcclk cycles. 01: 22 auxadcclk cycles. 10: 26 auxadcclk cycles. 11: 3 4 auxadcclk cycles. 5:3 unused 2:0 auxadc_ch[ 2:0 ] selects analog input channel to the a ux iliary adc. 000: auxin1, p in 72. 001: auxio2, p in 7 1. 010: auxio3, p in 7 0. 011: i nternal vptat voltage. 100: i nternal vcmli voltage. 101: i nternal vcmlq voltage. datasheet.in
ad9961/AD9963 rev. 0 | page 33 of 60 register name register address bit (s) parameter function 110: rxcml voltage. 111: not connected. any write to this register initiates an adc conversion cycle. aux adc msbs 0x78 7:0 aux adc [ 11:4 ] this is the 8 msbs of the most recent auxadc conversion result. aux ad c lsbs 0x79 7:4 aux adc [ 3:0 ] this is the 4 lsbs of the most recent auxadc conversion result. 3 conv_compl 0: indicates that the request auxiliary adc conversion is in progress. 1: indicates that the auxiliary adc conversion result is valid. 2:0 c han_sel[2:0] indicates the actual auxiliary adc input channel selected for the conversion. this should match the channel that was selected in the write to register 0x77 that initiated the conversion. aux adc ctrl 0 0x7a 7 aux adc_en 0: p owers down the a uxi liary adc clock. 1: enables the a uxiliary adc clock. 6 aux adc_resb 1: r esets the auxadc. a transition from 0 to 1 triggers the reset. the bit should be returned to 0 after issuing the reset. 5:3 unused 2:0 auxdiv[ 2:0 ] sets the frequency divi sion ratio of the input clock driving the clkp, clk n pins over the auxadcclk. 000: 2 56. 001: 128. 110: 4. 111: 2. the frequency of the auxadcclk should be less than 10 mhz. the sample conversion rate of the a uxadc is determ ined by the aux clk rate and conv_time. aux adc ctrl 1 0x7b 7 temp sns_en 1: e nables the on - chip temperature sensor. 6:5 unused 4:2 auxref_adj[ 2:0 ] adjustment for tuning the internal aux iliary adc reference voltage. 011: +18 mv. 010: +12 m v. 001: +6 mv. 000: default. 111: ?6 mv. 110: ?12 mv. 101: ?18 mv. 100: ?24 mv. 1:0 unused adc full - scale adj 0x7d 7:5 unused 4:0 rx_fsadj [4:0] this parameter adjusts the full - scale input voltage range of the rx path adcs. the peak -to - peak input voltage range can be set as follows : 10000: 1.25 v. 10001 : 1.27 v. 10010: 1.29 v. 10011: 1.31 v. 11111: 1.54 v. 00000: 1.56 v. 00001: 1.58 v. 01110: 1.873 v. 01111: 1.875 v. datasheet.in
ad9961/AD9963 rev. 0 | page 34 of 60 register name register address bit (s) parameter function rx adc trim ctrl 0x7e 7 unused 6 rxtri m_en 1: enables adc gain calibration. 5 rxtrim_fine 1: decreases the step size (increases resolution) of the gain calibration adjustment. 4 auxcml_en controls the buffers of internal bias points within each of the rx adcs to allow for checking of th is voltage. these voltages should read back about 0.9 v. 0: disables the buffers. 1: enables the buffers. 3:1 0 set to 000. 0 rx_dc 0: the adc common - mode buffer is active. this sets the adc inputs to the desired common - mode voltage through 10 k ? resistors to each single sided input. 1: disables the common - mode buffer. the buffer should be disabled whenever the user dc couples to the adc inputs. igain cal msbs 0x7f 7:0 rxi_trim[9:2] the rxi_trim[9:0] word is used to adjust the gain of the r eceive path i adc. these bits have no effect unless the rxtrim_en bit is set. the rxtrim_fine bit reduces the lsb size of the calibration word by ?. igain cal lsbs 0x80 7:3 unused 2:1 rxi_trim[1:0] 0 gaincal_eni 1: enables the gain calibration dac for the i rx adc. igain cal msbs 0x81 7:0 rxq_trim[9:2] the rxq_trim[9:0] word is used to adjust the gain of the receive path q adc. these bits have no effect unless the rxtrim_en bit is set. the rxtrim_fine bit reduces the lsb size of the calibration wo rd by ?. igain cal lsbs 0x82 7:3 unused 2:1 rxq_trim[1:0] bottom two lsbs of rxq_trim described in register 0x81 above. 0 gaincal_enq 1: enables the gain calibration dac for the q rx adc. igain cal lsbs 0xff 7:1 unused 0 update synchronously t ransfers adc configuration data from the global register set to the local adc register set and activates the changes. a 0 -to - 1 transition is required to initiate the transfer. 1: transfer adc parameters to adc to make changes active. datasheet.in
ad9961/AD9963 rev. 0 | page 35 of 60 receive path r x path general description the ad9961/AD9963 rx path s consist of dual, differential input, 100 msps adcs followed by an optional 2 decimation filter. the rx path also has digital offset and gain adjustments. rxi p trxd[ 1 1:0] rxin decim a tion scale dat a assembler rxqn i offset q offset rxq p trxiq trxclk lpf 1/2 lpf 1/2 i adc q adc 08801-112 figure 39 . receive path block diagram the dual adc paths share the same cloc k ing and reference circuitry to provide optimal matching characteristics. the adcs have a multi stage differe n tial pipelined switched capacitor architecture with output error correction l ogic. the adcs support if sampling frequencies up to 140 mhz, making them suitable for undersampling receivers. also, one of the adcs can be powered down and the digital interface can be placed into single adc mode. this flexibility makes the part well - suited for sampli ng real signals as well. receive adc operation the rx path analog inputs look into a nominal differential impedance of 4 k ?. the rx inputs are self - bi asing, so they can be either ac - coupled or direct coupled. the nominal dc bias level of the inputs is 1.4 volts. a buffered version of the bias voltage is available at the rxcml pin. this voltage can be used for biasing e xternal buffer circuits when dc coupling is required. for optimal dynamic performance, the analog inputs should be driven differentially. t he source impedances driving the rx inputs should be matched so that common - mode settling errors are symmetrical. the rx inputs can be driven with a single - ended source, but snr and sinad performance is degraded. adc reference voltage an internal differential voltage reference creates positive and negative reference voltages that define the full - scale input voltage of t he adcs. this full - scale input voltage range can be adjusted by means of the rx_fsadj [4:0] parameter in configuration register 0x7d. see the configuration registers section for more details on setting the voltage. the nominal input voltage range is 1.56 v . in general, a tradeoff can be made between linearity and snr. increasing the input voltage range leads to higher snr. decreasing the input voltage range leads to better linearity. rx bias the ad9 961/AD9963 provid e the user with the option to place a 10 k resistor between the r x bias pin and ground. this resisto r is used to set the master current reference of the adc core. the rxbias resistor should have a tolerance of 1% or better to preserve the accuracy of the a dc full - scale range. care should be taken in the layout to avoid any noise from coupling into the rxbias pin . rxcml the rxcml pin of the ad9961/AD9963 provides the user with a buffered version of the expected adc common - mode bias voltage. the rxcml output nominally is at 1.4 v. bypassing the rxcml output to analog ground maintains the stability of the output buffer and lowers the noise. to maintain the accuracy of the rxcml bias voltage, the current draw from the pin should be kept below 1 ma. reg 0x7e[0] reg 0x0f[1] rxip rxin rxqp rxqn rxcml 2k? 2k? ~1.4v ~1.4v iadc qadc cmbias ad9961/AD9963 pd en 2k? 2k? 08801-012 figure 40 . simplified s chematic of r x path i nputs differential input configurations optimum performance is achieved by driving the analog inputs in a differential input configuration. for baseband applications, the ada4937 differential driver pr o vides excellent performance and a flexible interface to the adc. figure 41 shows an ac - coupled input configuration. the vocm pin should be connected to a voltage that provides su fficient headroom for the output driver of the differential amp. usually, setting vocm to ? of the amplifier supply voltage is the optima l setting. placing source resistance in series with the amplifiers outputs isolates the amplifier from on - board parasit ic capacitances and leads to more stable operation. datasheet.in
ad9961/AD9963 rev. 0 | page 36 of 60 200? 1k? 1k? 200? 200? 200? 33? 33? 0.1f ada4937 vocm rxip rxin ad9961/ AD9963 0.1f 0.1f v cc +vin ?vin 08801-013 figure 41 . differential input configuration , ac -c oupled the output common - mode voltage of the ada4937 is set to match the common - mode voltage required by the adc by connecting the rxcml output to the vocm input of the amplifier. the rxcml output nominally is at 1.4 v. bypassing the rxcml output to analog ground maintains the stability of the output buffer and lowers the noise. 200? 200? 200? 200? 33? 33? 0.1f ada4937 vocm rxip rxin ad9961/ AD9963 +vin ?vin rxcml 08801-014 figure 42 . differential input c onfiguration, dc -c oupled at higher input frequencies , the amplifiers required to maintain the full dynamic power of the AD9963 requires considerable supply current. for higher frequency power sensitive applications , differential transformer coupling is the recommended input co n figuration. the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies b e low a few megahertz , and excessive signal power can also cause core saturation, which leads to distortion. in any configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. *c diff is optional. 1.25v p-p 33? 33? *c diff c 50 0.1f adt1-1wt 1:1 z ratio adc AD9963 rxi p c 0.1f rxin 08801-015 figure 43 . differential transformer coupled configuration single - ended input configuration driving the rx inputs with a single - ended signal typically limits the achievable adc performance. when using this configuration , best performance is achieved by maintaining a balanced impedance off each of the rx inputs as shown in figure 44. *c diff is optional. 1.25v p-p 33? 49.9 33? 25? *c diff c 49.9 0.1f adc AD9963 rxip c 0.1f rxin 08801-016 figure 44 . single -e nded input configuration interfacing to the adf4602 rx baseband outputs the adf4602 is an rf transceiver suitable for femtocell and other wireless communications applications. the adf4602 rx baseband outputs have a nominal output common - mode voltage that can be set to 1.4 v. the adf4602 can be dc - coupled to the AD9963. it is recommended that a first - order low - pass filter be placed between the two devices to reject unwanted high frequency signals that may alias into the desired baseband signal. 100? 100? 68pf 68pf adc AD9963 adf4602 rxip rxin rxbbi rxbbib 08801-118 figure 45 . adf4602 to AD9963 receive interface circuit in this application, the adf4602 is setting the common - mode input voltage of the AD9963 adcs. the input common - mode buffer of the AD9963 should be disabled (set r egister 0x7e , bit 1 = 1) to avoid contention with the adf4602 output driver. decimation filter an d digital offset decimation filter the i and q receive paths each have a bypassable 2 decimating low - pass fi lter. the half - band digital filter reduces the output sample rate by a factor of 2 while rejecting aliases that fall into the band of interest. t hese low - pass filters provide > 7 db of stop - band rejection for 40% of the output data rate. when used with quad rature signals, the complex output band is 80% of the quadrature output data rate. a graph of the pass - band response of the decimation filter is shown in figure 46. datasheet.in
ad9961/AD9963 rev. 0 | page 37 of 60 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0. 55 0. 60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 normalized frequenc y (relative to f dac ) magnitude (dbc) 08801-119 figure 46 . pass - band response of the r x path decimation filter the filter coefficients of the 2 decimation low - pass are shown in table 16. table 16. lower coefficient upper coefficient value h(1) h(43) 12 h(3) h(41) ?32 h(5) h(39) 72 h(7) h(37) ?140 h(9) h(35) 252 h(11) h(33) ?422 h(13) h(31) 682 h(15) h(29) ?1086 h(17) h(27) 1778 h(19) h(25) ?3284 h(21) h(23) 10364 h(22) 16384 adc digital offset adjustment the rx paths also have individual digital offsets that can be applied t o the data captured by the adcs. the offset is a 6 - bit digital value that is added directly to the lsbs of the adc output data. the offset values are configured by first addressing the adc by setting the appropriate address in register 0x05, then writing t he desired offset (in lsbs) into register 0x10. for example, to set offsets of +6 and ?2 to the i and q channels respectively, the register write sequence is : 1. write 0x01 into register 0x05. this addresses the i channel adc . 2. write 0x06 into register 0x10. this sets the iadc_offset value to +6 lsbs. 3. write 0x02 into register 0x05. this address es the q channel adc . 4. write 0xfe into register 0x10. this sets the qadc_offset value to ?2 lsbs. 5. write 0x01 into register 0xff. this u pdates the data path registers and applies the offset to the data. 6. write 0x00 into register 0x05. this returns the spi to the normal addressing mode. datasheet.in
ad9961/AD9963 rev. 0 | page 38 of 60 t ransmit path t x path general description the transmit section consists of two complete paths of interpolation filters stages, each followed by a high speed current output dac. a data assembler receives interleaved data from one of two digital interface ports, and de - interleaves and buffers the data before supplying the data samples into the two datapaths. the interpolation filter bank consists of three stages that can be completely bypassed or cascaded to provide 2 , 4 , or 8 i nterpolation. the supported clock rates for each of the interpolation filters and the transmit dacs are listed in table 1 . tx port trx port dat a assembler and fifo i dac i scale q scale i gain txvdd q gain q dac r fsadj lpf 1/2/4/8 lpf 1/2/4/8 txip txin txqp txqn txcm l refio 08801-017 figure 47 . transmit path block d iagram interpolation filters the i and q transm it paths contain three interpolation filters designated as int0, int1 , and srrc. each of the interpolation filters provides a 2 increase in output data rate. the filters ca n be completely bypassed or cascaded to provide 2 , 4 , or 8 upsampling ratios. th e interpolation filt ers effectively increase the dac update rat e while suppressing the images at the input date rate. this reduces the requirements on the analog output reconstruction filter. 1 0 int1 1 0 int0 1 0 srrc from fifo to dac srrc_b p 0x30[2] int0_b p 0x30[3] int0_scale 0x36[4:0] srrc_scale 0x35[4:0] int1_scale 0x37[4:0] int1_b p 0x30[4] 08801-018 figure 48 . block diagram of transmit datapath the digital filters should be cascaded such that int0 is enabled for an interpolation factor of 2, int 0 and int 1 should be enabled for an interpolation factor of 4, and int 0, int 1, and the srrc should be enabled for an interpolation factor of 8 . the int0 and int1 filters have bandwidths of 40% of the input data rate. over their usable bandwidth, the filters have a passband ripple of less than 0.1 db. the srrc has a roll - off factor of 0.22 with a 60 db stop - band attenuation. in 2 and 4 interpol ation modes, the interpolation filters have an image rejection of greater than 70 db. in 8 interpolation mode, the image rejection is greater than 65 db. the usable bandwidth of the filters i s typically limited by the stop - band attenuation they provide, r ather than the passband flatness. the transfer functions of the interpolation filters configured for 2, 4, and 8 interpolation ratios are shown in figure 49 through figur e 51 . ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 normalized frequenc y (relative to f dac ) magnitude (dbc) 08801-122 figure 49 . digital filter transfer function for 2 interpolation ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 normalized frequenc y (relative to f dac ) magnitude (dbc) 08801-123 figure 50 . digital filter transfer function for 4 interpolation ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 normalized frequenc y (relative to f dac ) magnitude (dbc) 08801-124 figure 51 . digital filter transfer fun ction for 8 interpolation datasheet.in
ad9961/AD9963 rev. 0 | page 39 of 60 interpolation filter coefficients the interpolation filters , int0 and int1 , are half - band filters implemented with a symmetric set of coefficients. every other coefficient (even coefficients) except the center coefficient is zero . the coefficient values for the three interpolation filters are listed in table 17 to table 19. table 17. coefficient v alues for int0 lower coefficient upper coeff icient value h(1) h(43) 12 h(3) h(41) ? 32 h(5) h(39) 72 h(7) h(37) ? 140 h(9) h(35) 252 h(11) h(33) ? 422 h(13) h(31) 682 h(15) h(29) ? 1086 h(17) h(27) 1778 h(19) h(25) ? 3284 h(21) h(23) 10364 h(22) 16384 table 18. coeff icient v alues for int1 lower coefficient upper coefficient value h(1) h(19) 26 h(3) h(17) ? 138 h(5) h(15) 466 h(7) h(13) ? 1314 h(9) h(11) 5058 h(10) 8191 table 19. coefficient v alues for srrc f ilter lower coefficient upper coefficient value h(1) h(53) ?2 h(2) h(52) ?2 h(3) h(51) 8 h(4) h(50) ?4 h(5) h(49) ? 21 h(6) h(48) 10 h(7) h(47) 44 h(8) h(46) ? 29 h(9) h(45) ? 79 h(10) h(44) 66 h(11) h(43) 123 h(12) h(42) ? 127 h(13) h(41) ? 183 h(14) h(40) 232 h(15) h(39) 2 51 h(16) h(38) ? 394 h(17) h(37) ? 326 h(18) h(36) 642 h(19) h(35) 401 h(20) h(34) ? 1034 h(21) h(33) ? 469 h(22) h(32) 1704 h(23) h(31) 523 h(24) h(30) ? 3160 h(25) h(29) ? 560 h(26) h(28) 9996 h(27) 16383 data flow and clock generation the transm it port txd[11:0] and txiq signals are captured from by the device with an input latch. the data is then formatted and buffered in an 8 - word deep fifo. the data exits the fifo and is processed by whichever interpolation filters are enabled. the data is the n sampled by the transmit dacs. the fifo absorbs any phase drift between the two clock domains that drive the transmit data. the data is read from the fifo by the rdclk signal. the rdclk signal is always the dacclk divided by the interpolation ratio, i. d ata is written to the fifo by the wrclk signal at the quadrature data input rate, f data . f data is equal to one - half the bus speed because the i and q samples are interleaved. figure 52 shows the block diagram of the transmit path data flow in full - duplex mode. also shown in the diagram are the input data clocking options and the clock doubler selections. datasheet.in
ad9961/AD9963 rev. 0 | page 40 of 60 write pointer i dac 12 12 read pointer 24 bits txclk dacclk i data path data format input latch reg 0 reg 1 reg 2 reg 3 reg 4 reg 5 reg 6 reg 7 24 fifo_offset reg 0x33[2:0] wrptr q dac 12 12 q data path rdptr = 0 fifo fifo reset and monitor fifo_ptr reg 0x34[7:0] txd[11:0] txiq 26 rdclk wrclk txsmpclk tx_bnry reg 0x31[0] tx_ifirst reg 0x31[1] txiq_hilo reg 0x31[2] txclk_md reg 0x31[1] txcki_inv reg 0x31[3] txcko_inv reg 0x31[6] txclk_md reg 0x31[0] 1 0 1 0 13 en en i 2 doubler tx_sdr reg 0x31[7] i = 1 txdbl_sel tx_dblpw[2:0] reg 0x39[0] reg 0x3e[5:3] * i denotes interpolation ratio 10 1 0 1 0 0 8801-150 figure 52. transmit path data flow and clock generation in full duplex mode the signal on the txclk pin can be configured as either an input or an output. this is configured by the txclk_md variable (register 0x31, bits[5:4]). whether configured as an input or an output, the txclk signal has the option of being inverted by configuring the txcki_inv or txcko_inv variables. the transmit path clock doubler is only used when all of the interpolation filters are bypassed (i = 1) and the transmit path is configured in bus rate mode (tx_sdr = 1). for more information about configuring the clock doubler, see table 22. transmit dac operation figure 53 shows a simplified block diagram of one of the transmit path dacs. each dac consists of a current source array, switch core, digital control logic, and full-scale output current control. the dac contains a current source array capable of providing a nominal full-scale current (i outfs ) of 2 ma. the output currents from the txip and txin pins are complementary, meaning that the sum of the two currents always equals the full-scale current of the dac. the digital input code to the dac determines the effective differential current delivered to the load. the dacs are powered through the txvdd pin and can operate over a 1.8 v to 3.3 v supply range. to facilitate interfacing the output of the ad9961/AD9963 directly to a range of common- mode levels, an internal bias voltage is made available through the txcml pin. the dac full-scale output current is regulated by the reference control amplifier and is determined by the product of a reference current, a programmable reference resistor, r ref , an internal programmable resistor, r set , and a pair of programmable gain scaling parameters. txvdd igain1[5:0] 0x68[5:0] igain2 0x69[5:0] 100a refio refio_adj[5:0] 0x6e[5:0] irset[5:0] 0x6a[5:0] txdata idac r ref r set tx1p tx1n txcml dacclk 08801-019 figure 53. simplified block diagram of i dac core transmit dac transfer function the output currents from the txip and txin pins are complementary, meaning that the sum of the two currents always equals the full-scale current of the dac. the digital input code to the dac determines the effective differential current delivered to the load. txip provides maximum output current when all bits are high. the output currents vs. daccode for the dac outputs are expressed as: outfs n txip i daccode i ? ? ? ? ? ? ? ? 2 (1) txip outfs txin iii ? ? (2) where daccode = 0 to 2 n ? 1. there are a number of adjustments that can be made to scale i outfs to provide programmability in the output signal level. datasheet.in
ad9961/AD9963 rev. 0 | page 41 of 60 transmit path gain adjustment adjusting the output signal level is implemented by scaling the full-scale output current of the transmit dac. there are four separate programmable parameters that can be used to adjust the full-scale output of the dacs; the refio voltage, the r set resistance, and the fine and coarse gain control parameters. adjusting the refio voltage there is a single reference voltage that is used by both the i and q channel dacs. the refio reference voltage is generated by an internal 100 a current source terminated into a programmable resistor, r ref . the nominal r ref resistance is 10 k resulting in a 1.0 v reference voltage. the resistance can be varied by adjusting the refio_adj[5:0] bits in register 0x6e. this adds or subtracts up to 20% from the r ref resistance and hence the refio voltage and the dac full-scale current. a secondary effect to changing the refio voltage is that the full-scale voltage in the auxiliary dacs also changes by the same magnitude. the register uses twos complement format in which 011111 maximizes the voltage on the refio node and 100000 minimizes the voltage. a curve illustrating the variation of refio voltage vs. refio_adj value is shown in figure 54. 0.7 0.8 0.9 1.0 1.1 1.2 1.3 0 8 16 24 32 40 48 56 refio adj v ref (v) 08801-020 figure 54. typical v refio voltage vs. refio_adj value the refio pin should be decoupled to agnd with a 0.1 f capacitor. if the voltage at refio is to be used for external purposes, an external buffer amplifier with an input bias current of less than 100 na should be used. an external reference can be used in applications requiring tighter gain tolerances or lower temperature drift. also, a variable external voltage reference can be used to implement a method for gain control of the dac output. the external reference is applied to the refio pin. note that the 0.1 f compensation capacitor is not required. the internal reference can be directly overdriven by the external reference, or the internal reference can be powered down. the input impedance of refio is 10 k when powered up and 1 m when powered down. table 20. reference operation reference mode refio pin register setting internal connect 0.1 f capacitor register 0x60, bit 6 = 0 (default) external apply external reference register 0x60, bit 6 = 1 (disables internal reference) adjusting the current scaling resistor each transmit dac has a resistor that is used to adjust the full- scale current. the nominal resistance is 16 k, which results in a full-scale current of 2 ma (when v refio equals 1.0 v). the 6-bit programmable values, irset[5:0] and qrset[5:0] (register 0x6a and register 0x6d), provide an output current adjustment range of 20% as shown in figure 55. 1.6 1.8 2.0 2.2 2.4 2.6 0 8 16 24 32 40 48 56 rset ( ? ) fsc (ma) 08801-021 figure 55. output current scal ing vs. irset and qrset values adjusting the gain parameters each transmit dac has coarse and fine gain control parameters for scaling the full-scale output currents. these adjustments change only the full-scale current of the dac and have no impact on the refio voltage. the coarse scale adjust (gain1) allows the nominal output current to be changed by 6 db in approximately 0.25 db steps. the adjustment range of the fine scale adjust (gain2) is about 2.5%. figure 56 and figure 57 show the resulting gain scaling vs. the gain1 and gain2 parameters. datasheet.in
ad9961/AD9963 rev. 0 | page 42 of 60 ?8 ?6 ?4 ?2 0 2 4 6 8 1 9 17 25 33 41 49 57 gain1 dbfs 08801-022 figure 56 . typical dac full - scale current vs. gain1 code 1.94 1.96 1.98 2.00 2.02 2.04 2.06 0 8 16 24 32 40 48 56 gain2 full-scale current (ma) 08801-023 figure 57 . typical dac full - scale curr ent vs. gain2 code transmit dac outputs the optimum noise and distortion performance s of the ad9961 / AD9963 are realized when they are configured for differential operation. the common - mode error sources of the dac outputs are significantly reduced by the common - mode rejection of a transformer or differential amplifier. these common - mode error sources include even - order distortion products and noise. the enhancement in distortion performance becomes more significant as the frequency content of the reconstru cted waveform increases and/or its amplitude increases . this is due to the first - order cancellation of various dynamic common - mode distortion mechanisms, digital feedthrough, and noise. r o r o + + txip txin txqp txqn txcml ? ? v ip v in v qp v qn v outq v outi r o r o 08801-024 figure 58 . basic transmit dac output circ uit figure 58 shows the most basic dac output circuitry. a pair of resistors, r o , are used to convert each of the compl e mentary output currents to a differential voltage output, v out x . because the current outputs of the dac are ve ry high impedance, the differential driving point impedance of the dac outputs, r out , is equal to 2 r o . figure 59 illustrates the output voltage waveforms. v peak v p v out v n v cm 0 ?v peak 08801-025 figure 59 . voltage o utput waveforms the comm on - mode signal voltage, v cm , is calculated as: o fs cm r i v = 2 the peak output voltage, v peak , is calculated as: o fs peak riv = with this circuit configuration, the single - ended peak voltage is the same as the peak differential output volt age. setting the txcml pin voltage the txcml pin serve s to change the dac bias voltages in the part, allowing it to operate w ith higher output signal common - mode voltages. when the output signal common mode is below 0.8 v, t h e tx cml pin should be tied dire ctly to agnd. when the output signal common mode is greater then 0.8 v, then the txc ml pin should be set to 0.5 v. the tx cml pin should be a low ac impedance source ( capacitive decoupling is recommended). when the txvdd supply is 1.8 v, the output signal c ommon - mode voltage should be kept close to 0 v and the tx cml pin should be connected directly to ground. when the txvdd supply is 3.3 v, the output signal common mode can be operated as high as 1.25 v. datasheet.in
ad9961/AD9963 rev. 0 | page 43 of 60 the circuit shown in figure 60 shows a typical output circuit co nfiguration that provides a non zero bias voltage at the txcml pin. resistance values of 499 ? for r l and 249 ? for r cml produce s a 2 v p- p differential output voltage swing with a 1.0 v output common - mode voltage and a voltage of 0.5 v supplied to the txcml pin. the 2 ma full - scale current flows through the 249 ? r cml creating the 0.5 v tx cml vo ltage. the decoupling capacitor, assures a low ac driving impedance for the txcml pin. r l txip txin ad9961/AD9963 r l + ? v out r txcml c r cml 65 66 62 08801-030 figure 60 . circuit for s etting txcml level u sing r cml transmit dac output circuit configurations the following section illustrate s some typica l output configu - rations for the ad9961 / AD9963 transmit dac s . unless otherwise noted, it is assumed that i outfs is set to a nominal 2.0 ma. for applications requiring the optimum dynamic performance, a differential output configuration is suggested. a dif ferential output configuration can consist of either an rf transformer or a differential op amp configuration. the trans - former configuration provides the optimum high frequency performance and is recommended for any application that allows ac coupling. th e differential op amp configuration is suitable for applications requiring dc coupling, signal gain, and/or a low output impedance. a single - ended output is suitable for applications where low cost and low power consumption are primary concerns. different ial coupling using a transformer an rf transformer can be used to perform a differential - to - single- ended signal conversion, as shown in figure 61 . the distortion performance of a transformer typically exceeds that available from standard op amps, particularly at higher frequencies. transformer coupling provides excellent rejection of common - mode distortion (that is, even - order harmonics) over a wide frequency range. it also provides electrical isolation and can deliver voltage gain without adding noise. transformers with different impedance ratios can also be used for impedance matching purposes. the main disadvantages of transformer coupling are low frequency roll - off, lack - of - power gain, and high output impedance. txip txin optional r diff ad9961/AD9963 65 66 r load 08801-031 figure 61 . differential output using a transformer the center tap on the primary side of the transformer must be connected to a voltage that keeps the voltages on txip and txin within the output common - mode voltage range of the device. note that the dc component of the dac output current is equal to i outfs and flows out of both txip and txin . the center tap of the transformer should provide a path for this dc current. in most applications, agnd provides the most conve - nient voltage for the transformer center tap. the complementary voltages appearing at txip and txi n (that is, v ioutp and v ioutn ) swing symmetrically around agnd and should be maintained with the specified output compliance range of the ad9961 / AD9963 . a differential resistor, r d iff , can be inserted in applications where the output of the transformer is connected to the load, r load , via a passive reconstruction filter or cable. r diff , as reflected by the transformer, is chosen to provide a source termination that results in a low voltage standing wave ratio ( vswr ) . note that approx imately half the signal power is dissipated across r diff . differential buffered output using an op amp a dual op amp (see the circuit shown in figure 62 ) can be used in a differential version of the single - ended buffer shown in figure 63 . the same r - c network is used to form a one - pole , differential, low - pass filter to isolate the op amp inputs from the high frequency im ages produce d by the dac outputs. the feed back resistor , r fb , determine s the differential peak - to - peak signal swing by the formula v out = 2 r fb i fs the minimum single - ended voltages out of the amplifier are, respectively, v min = v max ? r fb i fs the common - mode voltage of the differential output is determined by the formula v cm = v max ? r fb i fs datasheet.in
ad9961/AD9963 rev. 0 | page 44 of 60 ad9961/AD9963 txip txin r fb v out refio 63 65 txgnd 64 c f c r s r s r b r fb c f r b 66 + ? ada4841-2 + ? ada4841-2 08801-032 figure 62 . single - supply differential buffer sin gle - ended buffered output using an op amp an op amp such as the ada4899 -1 can be used to perform a single - ended current - to - voltage conversion, as shown in figure 63 . the ad9961/ AD9963 are config ured with a pair of series resistors, r s , off ea ch output. for best distortion performance, r s should be set to 0 . the feedback resistor, r fb , determines the peak - to - peak signal swing by the formula v out = r fb i fs the maximum and minimum voltages out of the amplifier are, respectively, v max = v refi o v min = v max ? i fs r fb ad9961/AD9963 txip txin r fb refio txgnd c f c +5v ?5v r s r s r b v out + ? ada4899-1 08801-033 63 65 64 66 figure 63 . single - supply single - ended buffer interfacing to the adf4602 the adf4602 is an rf transceiver suitable for femtocell and other wireless communications applications. the adf4602 tx baseband inp uts have a nominal input common - mode voltage requirement of 1.2 v. the AD9963 can be dc coupled to the adf4602 as shown in figure 64. when configured for a 2 ma full - scale current, the output swing of the circuit is 1 v ppd centered at 1.2 v. the txmcl pin is biased at 0.5 v to increase the headroom of the dac outputs. the txvdd and clk33v supplies must be supplied with 3.3 v to support this output compliance range from the dacs. 226? 249 0.1uf 249 249? 100k? 226? 249 249 249? 100k? txin txip txcm l auxio2 txqn auxio3 txqp txbbqb txbbq txbbi txbbib AD9963 adf4602 08801-142 figure 64 . AD9963 to adf4602 tx interface circuitry the optional 100 k? resistors connected between the auxio pins and the txin (and txqn) pins allow a dc offset to be provided to null out lo feedt hrough at the adf4602 outputs. datasheet.in
ad9961/AD9963 rev. 0 | page 45 of 60 device clocking clock distribution the clock distribution diagram shown in figure 65 gives an overview of the clocking options for each of the data converters. the receive path adcs and the transmit path dacs can be clocked directly from the clk p/clkn inputs or from the output of the on - chip dll. the auxiliary adc sampling clock is always a divided down version of the input clock. the auxiliary dacs are updated synchronously with the serial port clock and have no relationship with the clk p/clkn inputs. the best data converter perfo rmance is realized when a low jitter clock source drives the clk p/clkn inputs , and this signal is used directly (or through the on - chip divider) as the data converter sampling clocks. the adc and dac sampling clocks are independently selected to be derived from either the clk p/clkn input or from the dll output, dllclk. using dllclk as the data converter sampling clock signal may degrade the noise and sfdr performance of the converters. more information is given in the clock multipli cation using the dll section. the receive path adc has a d uty c ycle s tabilizer (dcs) to help make the adc performance insensitive to changes in the input clock duty cycle. the dcs can be bypassed. recommendations for using the dcs can be found in the clock duty cycle considerations section. the adc clock divider and the dll clock multiplication supports a variety of ratios between the receive path adc sampling clock and the transmit path dac sampling clock. table 21 details the specific values the device supports and which register bits are require configuration. table 21. clock tree configuration variables variable values address register bit (s) dcs_bp 0 or1 0x66 2 adcdiv 1, 2, 4 0x66 [1:0] adcclksel 0 or 1 0x71 7 dacclksel 0 or 1 0x71 6 n 1 to 6, 8 0x71 [3:0] m 1, 2, 3, , 32 0x72 [4:0] dlldiv 1, 2, 4 0x72 [6:5] auxdiv 2j, j = 1 to 8 0x7a [2:0] clk p clk n d ll ad cc lk d acc lk adcc lksel d ll d iv auxc lk dacc lksel extd ll c lk dc s_ bp 1 0 1 0 clk_pd adc dac auxadc dll c lk dc s 0 1 m n aux d iv adcd iv 08801-143 figure 65 . clock distribution diagram datasheet.in
ad9961/AD9963 rev. 0 | page 46 of 60 drivin g the clock input for optimum performance, the ad9961/AD9963 clock inputs (clkp and clkn ) should be clocked with a low jitter, fast rise time differential signal. this signal should be ac - coupled to the clkp and clkn pins via a transformer or capacitors. t he clk p/clkn inputs are internally biased and require no external bias circuitry . figure 66 through figure 69 show preferred method s for clocking the ad9961/AD9963 . 10 0 ? 0.1f 0.1f 0.1f 0.1f 50?* 50?* clk clk *50 ? resistors are optional. clk_n clk_ p adc AD9963 lvds driver clk+ clk? ad9510/ad95 1 1/ ad9512/ad9513/ ad9514/ad9515/ ad9516/ad9518 08801-035 figure 66 . differential lvds sample clock in applications where the receive analog input signals and the transmit analog output signals are at low frequencies, it is acceptable to drive the sample clock inputs with a single - ended cmos signal. in such applications, clkp should be driven directly from a cmos gate, and the clkn pin should be bypassed to ground with a 0.1 f c a pacitor in parallel with a 39 k ? resistor (see figure 67 ). a series termination resistor off the clock driver output may improve the dynamic response of the driver. 0.1f 50 ? clk clk 0.1f 0.1f clk_n clk_p adc AD9963 optiona l 100? 39k? cmos driver clk+ ad9510/ad95 1 1/ ad9512/ad9513/ ad9514/ad9515/ ad9516/ad9518 08801-036 figure 67 . single - ended 1.8 v cmos sample clock 10 0 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? 50 ?* 50 ? * clk clk *50 ? resistors are optional. clk_n clk_p adc AD9963 pec l driver clk+ clk? ad9510/ad95 1 1/ ad9512/ad9513/ ad9514/ad9515/ ad9516/ad9518 08801-037 figure 68 . differential pecl sample c lock 0.1f 0.1f 0.1f 0.1f schottky diodes: hsm2812 clk+ 50? clk_n clk_p mini-circuits? adt1-1wt, 1:1z xfmr ad c AD9963 08801-138 figure 69 . transformer c oupled clock note that the 39 k ? resistor shown in the cmos clock driver example shifts the clk _n input to about 0.9 v. this is optimal when the cmos driver is supplied from a 1.8 v supply. a 2.5 v cmos driver may also be used. in this case , the minimum clk33v supply voltage should be 2.5 v. the 39 k? resistor should be removed in this case. connec ting clkn to ground with just a 0.1 f capacitor result s in the clkn voltage being biased to about 1.2 v. clock duty cycle considerations the duty cycle of the input clock should be maintained between 45% and 55%. duty cycles outside o f this range affect s the d ynamic performance of the adc. this is especially true at sample rates greater than 75 mhz. it is recommended that the duty cycle stabilizer (dcs) be used at clock rates above 75 mhz to ensure the sampling clock maintains the proper duty cycle inside the device. below 75 mhz, the dcs should be bypassed. the dcs is bypassed by setting r egister 0x66, b it 2 high. clock multiplication u sing the dll the ad9961/AD9963 contain a recirculating dll , as shown in figure 70. this circuit allows the incoming clk signal (refclk) to be multiplied by a programmable m/n factor. this provides a means of generating a wide range of dll output clock (dllclk) frequencies. the dllclk signal can be used for either the receive adc sampling clock, the t ransmit dac sampling clock , or both. the extdllclk signal can be programmed to appear on the txclk pin or trxclk if desired. m charge pump dll_resb reg 0x75[3] 1 0 select logic phase detector dlldiv n refclk dllclk extdllclk mclk dllfilt pin 54 delay line dll_en reg 0x60[7] dll_ref_en reg 0x71[4] dlllocked reg 0x72[7] dllbiaspd reg 0x61[5] m[4:0] reg 0x72[4:0] dlldiv[1:0] reg 0x72[6:5] m[3:0] reg 0x71[3:0] 08801-148 figure 70 . function al block diagram of clock multiplier dll datasheet.in
ad9961/AD9963 rev. 0 | page 47 of 60 the dll is comp osed of a ring oscillator mad e from a programmable delay line. the ring oscillator output signal is labeled as mclk. the mclk signal is set to oscillate at a frequency m times greater than the refclk signal. the dll output clock, dllclk, is the mclk signal divided by a programmable fa ctor, n. m can be set to values from 1 to 32 and n can be set to values from 1 to 6 and 8. dll frequency locking range the dll frequency lock range is determined by the output frequency of the ring oscillator, mclk. the dll locks over an mclk frequency ran ge of 100 mhz to 310 m h z. verifying that the dll is locked can be done by polling the dll_l ocked bit (r egister 0x72, b it 7). dll filter considerations the dll requires an external loop filter between the dllfilt pin ( p in 54) and ground for stable operation . the circuit diagram in figure 71 shows the recommended dll filter configuration. the external components should be placed as close as possible to the device pins. it is important that no noise be coupled into the filter circuit or dll output clock jitter performance is degraded. r z 22.5 ? c p c z 820pf 68nf dllfi lt 08801-039 figure 71 . recommended dll loop filter dll start - up routine to enable the dll, three bits should be set. the dll_en bit (r egister 0x60, b it 7) and the dll _ ref_en bit ( r egister 0 x71, b it 4) should be set to 1 and the dllbias_pd bit ( register 0x61, b it 5) should be set to 0 . the clk input signal should be stable. the dll_resb bit should be asserted low for a minimum of 25 s, and then brought inactive (high) to start the frequency acquisition. the dll takes several refclk cycles to acquire lock. the dll_l ocked bit can be queried to verify the dll is locked. configuring the cloc k doublers the receive and transmit data path each have a clock doubler used for clocking data through the device. these clock doublers are only used in single data rate clocking mode, when there is no interpolation or decimation being used. these doublers should be configured according to the following guidelines. register 0x3a, register 0x3b, and register 0x 3c configure the operating points of the doublers and should be initialized with the following values: 0x3a = 0x55, 0x3b = 0x55, 0x3c = 0x 00 the clock doubler mode and pulse widths should be configured based on the dac and adc sample rates. these should be configured according to table 22 . table 22. clock doubler configuration guidelines dacclk/ aux adcclk freq (mhz) txdblsel reg ister 0x39, bit 0 tx _ dblpw[2:0] reg ister 0x3e, bit s [5:3] rxdblsel reg ister 0x39, bit 1 rx _ dblpw[2:0] reg ister 0x3e, bit s [2:0] dcs_bp 1 register 0x66, bit 2 0 to 15 0 111 0 111 1 15 to 30 1 x 2 0 111 1 30 to 45 1 x 2 0 110 1 45 to 55 1 x 2 0 101 1 55 to 65 1 x 2 0 100 1 65 to 70 1 x 2 0 011 1 70 to 70 1 x 2 1 x 2 0 1 the dcs_bp bit should be set based on the auxadcclk frequency. 2 x = dont care. datasheet.in
ad9961/AD9963 rev. 0 | page 48 of 60 digital interfaces the ad9961/AD9963 have two parallel interface ports, the tx port and the t rx port. the operation of the ports depends on whether the device is configured for full - duplex or half - duplex mode. in full - duplex mode , the t rx and t x port operate in dependently. the tr x port outputs samples from the receive path and t he t x port accepts incoming samples for the transmit port. in half - duplex mode , the tr x port outputs samples from the receive path and accepts incoming samples for the transmit path. the t x port is disabled. the operation of the digital interface is detai led in the sections that follow. tr x port operation (full - duplex mode) in full -d uplex mode, the trx port sources the data from the ad9961/AD9963 i and q receive channels. the interface consists of an output data bus (trxd[11:0]) that carries the interleave d i and q data. the data is accompanied by a qualifying output clock (trxclk) and an output signal (trxiq) that identifies the data as from either the i or q channel. the m aximum guaranteed data rate is 200 msps . the basic timing diagram for the r x path i s shown in figure 72 . by default, the time - aligned trxd[11:0] and trxiq output signals are driven on the rising edge of the trxclk signal. the t od parameters are specified in table 23. trxiq trxd[ 1 1:0] trxclk i0 i1 q0 q1 08801-154 t od1 figure 72 . receive path timing diagram (bus rate clock mode) an additional configuration bit, rxclkph, is available to invert the trxclk. in this case, the trx data and the trxiq signals are driven out on the falling edge of trxcl k and t od is measured with respect to the falling edge of trxclk. the analog signals are sampled simultaneously , creating a quadrature pair of data. this creates two possible data pairing orders on the output bus, i data followed by q data, or q data follo wed by i data. there are also two possible ways to align the bus data with the trxiq signal, i data aligned with trxiq being high or i data aligned with trxiq being low. the iq pairing and data to trxiq alignment relationships create four possible timing m odes. the ad9961/AD9963 enable any of these four modes to be sourced from the device. the data pairing order is controlled by the rx_ifirst bit. the phase relationship between the r x data and the rxiq signal is controlled by the rxiq_hilo bit. the two prog ramming options produce the four timing diagrams shown in figure 73 . i1 i0 q0 trxiq trxd [11 : 0] trxd [11 : 0] trxd [11 : 0] trxd [11 : 0] q1 i 2 q2 q1 q0 i1 i2 q2 i3 q1 i0 i1 q2 i2 q0 i1 q1 q2 i2 q3 i0 rx _i f ir st = 1 rxiq_hilo = 1 rx _i f ir st = 1 rxiq_hilo = 0 rx _i f ir st = 0 rxiq_hilo = 1 rx _i f ir st = 0 rxiq_hilo = 0 08801-045 figure 73 . receive path data pairing options the output clock on trxclk can also be configured as a double data rate (ddr) clock. in t his mode the output clock is divided by 2 and samples are placed on the trxd[11:0] bus on both the rising and falling edges of the trxclk. figure 74 shows the timing. trxiq trxd[ 1 1:0] t od2 i0 i1 q0 q1 08801-156 trxclk figure 74 . receive path timing diagram (ddr clock mode) table 23. maximum output delay between trxclk/ trxd[11:0] and trxiq signals from ? 40 c to +85 c parameter min max min max units drive strength register 0x63 = 0x00 register 0x63 = 0xaa t od1 0.55 0.93 0.36 0.57 ns t od2 0.42 0.67 0.20 0.35 ns single adc mode the receive port can be operated with only one of the adcs operational. i n this mode the trxclk signal can operate in either bus r ate c lock mode or d ouble d ata r ate c lock mode. the trxiq pin indicates which adc is active. figure 75 to figure 78 show the timing options available. datasheet.in
ad9961/AD9963 rev. 0 | page 49 of 60 trxiq trxd[ 1 1:0] trxclk i0 i1 t od2 08801-157 figure 75 . rx timing, i adc o nly, bus rate clock mode trxiq trxd[ 1 1:0] trxclk q0 q1 t od2 08801-158 figure 76 . rx timing, q adc o nly, bus rate clock mode trxiq trxd[ 1 1:0] trxclk i0 i1 t od2 08801-159 figure 77 . rx timing, i adc o nly, ddr clock mode trxiq trxd[ 1 1:0] trxclk q0 q1 t od2 08801-160 figure 78 . rx timing, q adc o nly, ddr clock mode in addition to the different timing modes listed in figure 75 to figure 78 , the input data can also be deli vered from the device in either u nsigned binary or twos compl e ment format. the format type is chosen via the rx_bnry configuration bit. tx port operation (f ull - duplex mode) the t x port operates with a qualifying clock that can be configured as either an i nput or an output. the input data (txd[11:0]) must be accompanied by the txiq signal which identifies to which transmit channel (i or q) the data is intended. by default, the data and txiq signals are latched by the device on the rising edge of txclk. the timing diagram is shown in figure 79 txiq txd[11:0] txclk t su t hd 08801-051 figure 79 . tx port timing diagram (data rate clock mode) the set up and hold time requirements for the t x port in d ata r ate clock m ode are given in table 24. the input samples to the device are assembled to create a quadrature pair of data. the data can be arranged in two possible data pairing orders and with two possible data to txiq signal phase relationships. this creates four possible timin g modes. the ad9961/AD9963 can be configured to accept data in any of these four modes. the data pairing order is controlled by the tx_ifirst bit. the data to txiq phase relationship is controlled by the txiq_hilo bit. the two programming options produce t he four timing diagrams shown in figure 80 . i1 i0 q0 txiq txd [11 : 0] txd [11 : 0] txd [11 : 0] txd [11 : 0] q1 i2 q2 q1 q0 i1 i2 q2 i3 q1 i0 i1 q2 i2 q0 i1 q1 q2 i2 q3 i0 tx _i f ir st = 1 txiq_hilo = 1 tx _i f ir st = 1 txiq_hilo = 0 tx _i f ir st = 0 txiq_hilo = 1 tx _i f ir st = 0 txiq_hilo = 0 08801-052 figure 80 . transmit path data pairing options in addition to the different timing modes listed above, the input data can also be ac cepted by the device in eit her u nsigned binary or twos complement format. the format type is chosen via the tx_bnry configuration bit. datasheet.in
ad9961/AD9963 rev. 0 | page 50 of 60 the tx port has an optional double data rate (ddr) clock mode. in ddr mode, the transmit data is latched on both the rising and falling edges of tx clk. the polarity of the edge identifies to which channel the input data is intended. in this mode, the txiq signal is not required. the interleaved d igital data for the i and q dacs is accepted by the t x bus (txd([11:0]). the data must be presented to the device such that it is stable throughout the set up and hold times, t s and t h , around both the risi ng and falling edges of the txclk signal. a detailed timing diagram is shown in figure 81. txd[11:0] txclk t su t hd t su t hd 08801-053 figure 81 . tx port timing d iagram (ddr clock mode) in ddr mode, the txclk signal is always an input and must be supplied along with the data. the setup and hold time requirements for the t x port in ddr mode are given table 24 table 24. tx port se tu p and h old t imes f rom ? 40 c to +85 c 1 tx port operating mode drvdd = 1.8 v drvdd = 3.3 v t su ( min ) t hd (min) t su ( min ) t hd (min) unit txclk_md = 01 ? 0.02 + 2.60 + 0.29 + 1.99 ns txclk_md = 10 , txdblsel = 1 ? 1.04 + 4.24 ? 0.28 + 3.92 ns txclk_md = 10 , txdblsel = 0 ? 0.61 + 4.76 ? 0.14 + 4.82 ns 1 spec ification s are preliminary and subject to change. the input samples to the device are assembled to create a quadrature pair of data. the two possible data pairing orders and two possible data to txiq signal phase relationships create four possible timing modes. the ad9961/AD9963 can be configured to accept data in any of these four modes. the data pairing order is controlled by the tx _ ifirst bit. the data to txiq phase relationship is controlled by the txiq _hilo bit. the two programmi ng options produce the four timing diagrams shown in figure 82 . i1 i0 q0 tx clk txd [11 : 0] txd [11 : 0] txd [ 11 : 0] t xd [11 : 0] q1 i2 q2 q1 q0 i1 i2 q2 i3 q 1 i0 i1 q2 i2 q0 i1 q1 q2 i2 q3 i0 txif ir st = 1 txiq ph = 1 txif ir st = 1 txiq ph = 0 txi f ir s t = 0 txiq ph = 1 txif ir st = 0 txiq ph = 0 08801-054 figure 82 . transmit path timing modes (ddr mode) half - duplex mode the ad9961/AD9963 offer a half - duplex mode enabling a reduced width digit al interface. in half - duplex mode, the transmit and receive ports are multiplexed onto the trxd, trxiq , and trxclk lines. the direction of the bus can be controlled by either the txiq/txnrx pin (for the rest of this section referred to as simply the txnrx pin) or the serial port configuration registers. the operation of the transmit and receive ports in half - duplex mode is very similar to the way they operate in full - duplex mode. in half - duplex mode, the interface can be configured to operate with a single clock pin, or with two clock pins. when in rx mode (sourcing data) the trx port operates the same in half - duplex mode as it does in full duplex. when in t x mode , the txiq and txd[11:0] signals are mapped onto the trxiq and trxd[11:0] pins respectively. th e txclk pin is mapped to the trx clk pin in one - clock mode and remains on the txclk pin in two - clock mode. therefore, in one - clock mode , the trxclk pin carries the rxclk signal when set in the r x direction and the txclk signal when set in the t x direction. in two - clock mode, the trx pin carries the rxclk signal and the txclk pin carries the txclk signal regardless of the bus direction. by default, the clocks sourced by the device are only present when the corresponding direction of the bus is active. setup a nd hold times for the trx p ort are shown in table 25. table 25 . tr x port s et u p and h old t imes f rom ? 40 c to +85 c tr x port operating mode drvdd = 1.8 v drvdd = 3.3 v t su ( min ) t hd (min) t su ( min ) t hd (min) units txclk_md = 01 + 0.73 + 1.61 + 0.44 + 1.90 ns t xclk_md = 10, txdblsel = 1 ? 1.66 + 5.84 ? 0.96 + 4.55 ns txclk_md = 10, txdblsel = 0 ? 1.40 + 6.6 2 ? 1.15 + 5.11 ns datasheet.in
ad9961/AD9963 rev. 0 | page 51 of 60 table 26 shows the operating modes v s. s erial p ort configuration bits . table 26. tr x bus o peration via serial port txen rxen trxd bus direction tx bus function 0 0 hi gh -z hi gh -z 0 1 rx hi gh -z 1 0 tx hi gh -z 1 1 rx hi gh -z table 27 shows the operating modes of the trxd bus as a function of the tx n rx signal. the tx bus is high impedance in half - duplex mode. table 27 . rx bus o peration via txnrx p in txnrx state trxd bus direction tx bus function 0 rx hi gh -z 1 tx hi gh -z the timing of the bus turnaround is shown in the figure 83 and figure 84. trxiq high-z high-z trxd[11:0] t txrdy txnrx 08801-055 figure 83 . half- duplex bus turna round, rx to tx trxiq high-z high-z trxd[11:0] t txrdy txnrx 08801-056 figure 84 . half- duplex bus turna round, tx to rx datasheet.in
ad9961/AD9963 rev. 0 | page 52 of 60 auxiliary converters the ad9961/AD9963 have two fast settling servo dacs, along with an analog input and two a nalog i/o pins. all of the a uxiliary converters run off a dedicated supply pin. the input and output compliance ranges depend on the voltage supplied. auxiliary adc the a uxiliary adc is a 12 - bit sar converter that is accessed and controlled through the serial port registers ( re gister 0x77 through register 0x7b). the adc voltage reference and clock signals are generated on chip. the a uxiliary adc is preceded by a seven - input multiplexer. the adc inputs can be connected to either the auxin1, auxio2, auxio3 input pins, or one of fo ur internal signals as shown in figure 85 . aux dac10a auxin1 auxio2 auxio3 vcmlq vrxcml v ptat vcmli /r clk 2.5v auxref auxadcc lk 11 0 10 0 10 1 01 1 00 0 00 1 01 0 reg 0x 77 [2:0] sel reg 0x7a[2:0] vint 11 1 aux dac10b aux dac 08801-057 figure 85 . block diagram of auxiliary adc circuitry conversion clock the a uxiliary adc conversion clock is generated through a programmable binary division of the clk input signal. the frequency of the adc conversion clock is programmable and can be calculated from the following equation: r f f clk auxclk = w here r is programmed through r egister 0x7a, bits[2:0]. for best performance and lowest power consum ption, the conversion clock speed should be set to the lowest speed that meets the system conversion time requirements. the maximum allowable a uxiliary adc clock speed is 10 m hz. voltage reference the a uxiliary adc has an internal, temperature stable, 2.5 v reference. this results in an input voltage range of 0 v to 3.2 v. when using the internal voltage reference, the auxadcref pin should be decoupled to agnd through a 0.22 f capacitor. the auxadcref pin can be used as a reference output to external devi ces, but the current load on the pin should be limited to sourcing less than 5 ma and sinking less than 100 a. for systems with tight accuracy requirements, a higher accuracy external reference can be used to source a voltage into the auxadcref pin. the i nput voltage range for external voltage references is from 1.0 v to 2.5 v. the input impedance of the auxadcref pin is 100 k?. the full - scale input voltage of the adc is a function of the voltage reference as: auxref auxfs v v = 5.2 2.3 analog inputs the adc can be configured to sample one of eight analog inputs. the input is selected through the channels select bits (r egister 0x77, b its [2:0] ). these eight signals are described in table 28. table 28. aux iliary adc channel selections channel select signal description 000 auxin1 pin 72. 001 auxio2 pin 7 1. the a ux iliary dac10a should be disabled when using this pin as an input. 010 auxio3 pin 7 0 . the a ux iliary dac10b should be disabled when using this pin as an input. 011 vptat voltage proportional to absolute temperature scaled to 0.2 k per lsb. therefore, the temperature in degrees c is: 2.273 5 _ ) (c o ? = code adc t 100 vcmli common mode level of the i and q r x adc buffers. should measure approximately 0.9 v. th e buffer must be enabled ( s ee c onfiguration r egister 0x7e). 101 vcmlq 110 rxcml the rxcml output voltage on p in 10. this should measure approximately 1.4 v. 111 gnd should measure 0 v. when selected, i nput pin 70, pin 71, and pin 72 are connected to the sampling cap of the auxiliary adc. therefore, the circuits driving these inputs need to recover to the desired accuracy from having a discharged 10 pf capacitor connected to it at the initiation of the conversion, within the sampling window. a programm able delay ( r egister 0x7b, bits[1:0] ) can be added to the conversion cycle time to allow additional settling time of the input. if the adc input is driven from a low source impedance, like the output of an op amp, a 20 - cycle conversion time should yield go od results. higher impedance sources may require the 34 - cycle conversion time to fully settle. where the conversion cycle time is not an issue, it is recommended that the full 34 - cy cle conversion time be used. conversions where the input multiplexer is swi tched between inputs require a longer conversion cycle time than consecutive conversions from the same multiplexer input. datasheet.in
ad9961/AD9963 rev. 0 | page 53 of 60 digital output coding the digital output coding is straight binary. the ideal transfer characteristic for the a uxiliary adc is shown in figure 86 . 000 ... 000 000 ... 001 000 ... 010 111 ... 101 111 ... 110 111 ... 111 adc code analog input +0.5 lsb 1 lsb +v fs ? 1.5 lsb +v fs ? 1 lsb 08801-058 figure 86 . auxiliary adc t ransfer f unction aux iliary adc conversion cycle a conversion is initiated by writing to spi r egister 0x77. the conversion starts on the first rising edge of the a uxadcclk following a write to r egister 0x77 (s erial port register writes are completed on the e ighth rising edge of sclk during the data word write cycle ). the conversion take s from 20 to 34 auxadcclk cycles to complete depending on the conversion time setting programmed in r egister 0x7 7. in most cases, the adc throughput is a function of both the serial port clock rate and the adc conversion time. figure 87 shows a typical t iming scenario for an a uxiliary adc conversion period. the scenario shows the write that initiates the conversion, followed by the read that retrieves the conversion result. in some cases , it may be required to add a wait time between the write and read to ensure that the conversion is complete. the wait time depend s on the adc conversion cycle time and the speed of the serial port clock. the minimum wait time is calculated as: sclk auxadcclk wait t tnt ? + 7 )1( w here n is the number of a ux iliary adc clock cycles that result from the conversion time setting in r egister 0x7b. t sclk is the serial port clock period. a negative wait time indicates no wait time is required. write instr. write instr. read instr. data reg 0x77 adc conversion adc conversion serial port wait wait data reg 0x78 data reg 0x77 data reg 0x79 aux adc cycle 1 aux adc cycle 2 08801-059 figure 87 . timing s cenario for auxiliary adc c onversion cycle it should be noted that after initial power - up or recovery from power - down, the adc need s about 100 s to stabilize. in many cases , the results of the first conversion should be discarded in order for the auxiliary adc to reach an optimum operating condition. auxil iary dac s the AD9963 has two 10 - bit auxiliary dacs and two 12 - bit auxiliary dacs suitable for calibration and control functions. the dacs have voltage outputs with selectable full - scale voltages and output ranges. the auxiliary dacs are configured and upda ted through the serial port interface. 10- bit auxiliary dacs the two 10 - bit dacs have identical transfer functions and are output on the auxio2 and auxio3 pins. the two dacs can be independently enabled and configured. the dacs have five selectable top - of - scale voltages and four selectable output ranges, which result in 20 possible transfer functions . + ? daccode[9:0] avdd dac10_rng 0.5v 16k? auxio dac10_rng: 00 = 2.0v = 124a ifs 01 = 1.5v = 93a ifs 10 = 1.0v = 62a ifs 11 = 0.5v = 31a ifs r top dac10_top: 000 = 1.0v = 16k ? 001 = 1.5v = 8.0k ? 010 = 2.0v = 5.3k ? 011 = 2.5v = 4.0k ? 100 = 3.0v = 3.2k ? ispan 08801-060 figure 88 . simplified circuit diagram of the 10 -b it auxiliary dac the circuit is most easily analyzed using superposition of two in puts to the op amp, the 0.5 v reference voltage , and the programmable current source. the foll owing equation describes the no - load output voltage: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??+= span top out i daccode r v v 1024 5.0 k165.0 the daccode (see register 0x4 9 and register 0x4 a for dac10a and register 0x4 6 and reg ister 0x4 7 for dac10b) is interpreted such that i span is full scale at 0x000 and zero at 0x3ff . this leads to an increasing output voltage with increasing code as shown in figure 89 and figure 90. the fiv e selectable gain setting resistors of 3.2 k? , 4.0 k? , 5.3 k? , 8.0 k?, and 16 k? result in full - scale output voltage levels of 3.0 v, 2.5 v, 2.0 v, 1.5 v and 1.0 v respectively. the four selectable full - scale currents of 31 a, 62 a, 93 a and 124 a res ult in voltage output spans of 0.5 v, 1.0 v, 1.5 v, and 2.0 v, respectively. datasheet.in
ad9961/AD9963 rev. 0 | page 54 of 60 the curves in figure 89 represent four of the possible dac transfer functions with the full - scale voltage of 3.0 v and spans of 0.5 v , 1.0 v , 1.5 v, an d 2.0 v. the curves in figure 90 represent four of the possible dac transfer functions with the full - scale voltage of 1.5 v and spans of 0.5 v , 1.0 v , 1.5 v, and 2.0 v. note that the 2.0 v span results in clamping at the lower end of the scale at 0 v where the equation result s in negative output voltages. 0.5 1.0 1.5 2.0 output vo lt age (v) code 2.5 3.0 3.5 0 128 256 384 512 640 768 896 1024 rng00 rng01 rng10 rng11 08801-061 figure 89 . auxdac10 voltage output vs. digital code, v top = 3.0 v (r top = 3.2 k?) 0 0.25 0.50 0.75 output vo lt age (v) code 1.25 1.75 1.00 1.50 2.00 0 128 256 384 512 640 768 896 1024 rng00 rng01 rng10 rng11 08801-062 figure 90 . auxdac10 voltage output vs. digital code, v top = 1.5 v (r top = 8.0 k?) 12- bit auxiliary dacs the two 12 - bit dacs have similar transfer functions and are output on the dac12a and dac12b pins. the two dacs can be independently enabled and configured. figure 91 sh ows a simplified schematic of the 12 - bit auxiliary dac. au x33v au xdacr ef 2.3 ? r r r top 1 0 vref dac 12 dac 1 2t op: 0 = r top = 0.8r 1 = r top = 2.3r 0 t o vref refio dacc ode 08801-063 figure 91 . simplified s chematic of the 12 -b it auxiliary dac note that vref can be derived from a 1.0 v bandgap reference or be ratiometric with the aux33v supply. an additio nal gain stage follows the dac that sets the final full - scale output voltage . the following equation describes the no load output voltage: u 1024 daccode vv fs out w here v fs is set with the combination of bits shown in table 29 . table 29. 12 -b it aux iliary dac full - scale voltage s election auxdac _ ref dac1 0 x_rng 1 v fs 0 0 aux33v 0 1 0.54 aux33v 1 0 3.3 v 1 1 1.8 v 1 x = a or b . the curves in figure 92 show the two transfer functions when using the internal 1.0 v bandgap reference. 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 128 256 384 512 640 768 896 1024 output vo lt age (v) code v fs = 3.3v v fs = 1.8v 08801-064 figure 92 . auxdac 12 voltage output vs. digital code datasheet.in
ad9961/AD9963 rev. 0 | page 55 of 60 power supplies the ad9961/AD9963 p ower distribution s are shown in f igure 93 . the functional blocks labeled rx anlg, rx adcs, spi and d ig ital c ore, c locking , and dll operate from 1.8 v supplies. the functional blocks labeled tx dacs, aux dacs and d igital i/o operate over a supply voltage range from 1.8 v to 3.3 v. the a ux iliary adc operates from a 3.3 v supply. aux adcs aux dacs rx anlg dl l clocking spi and digi tal core rx adcs ad9961/AD9963 tx dacs digi tal i/o ldo ldo ldo ldo ldo aux33v rx18v rx33v rx18vf txvdd(2) dll18v clk18v dvdd18v dr vdd(3) 08801-065 figure 93 . ad9961/AD9963 power distribution block diagram the 1.8 v only blocks can be supplied directly with 1.8 v by using the rx18v, rx18vf, dll18v, clk18v , and dvdd18v supply pins. in this mode , the on - chip voltage regulators must be disabled. to provide optimal esd protection for the device, the inputs of the ldo regulators should not be left floating. when unused, the ldo regulator inputs should be tied to one of the ldo outputs ( f or example, if rx33v is unused, tie rx33v to either rx18v or rx18vf). when the ldo regulators are used, the rx18v, rx18vf, dll18v, clk18v , and dvdd18v pins should be decoupled to ground with a 0.1 f or larger capacitor . the ldo inputs can operate over a rang e from 2.5 v to 3.3 v. the ldo_en pin ( p in 14) is a three - state input pin that controls the operation of the ldos. when ldo_en is high, all of the ldos are enabled. when ldo_en is low, all of the ldos are disabled. when ldo_en is floating or approximately drvdd/2, only the dvdd18v ldo is enabled. all of the ldos except the dvdd18v ldo can be independently disabled through serial port control as well by writing to r egister 0x61. the three drvdd pins are internally connected together, therefore , these pins m ust be connected to the same voltage. the voltage applied to these pins affect s the timing of the device as noted in the digital interfaces section. the txvdd and aux33v supplies can operate over a range from 1.8 v to 3.3 v. it sh ould be noted that the auxiliary adc requires aux33v to be 3.3 v for operation. the performance of the tx dacs vary with the txvdd supply as indicated in the table 1 and figure 4 to figure 11. power supply configu ration examples there are numerous ways of configuring the power supplies powering the ad9961/AD9963. two power supply configuration examples are shown in figure 94 and f igure 95 . figure 94 shows a 3.3 v only power supply configuration. in this case, all of the internal circuits that require 1.8 v supplies are powered from the on - chip regulators. the ldo_en pin is set high, and all of the interna l ldos are enabled. the transmit dac, a uxiliary converters , and i/o pads run from a 3.3 v supply . aux33v rx33v rx18v reg 0x61 = 0x00 3.3v ad9961/AD9963 rx18vf dr vdd ldo_en dvdd18 dll18v clk18v clk33v txvdd 08801-066 figure 94 . 3.3 v only supply c onfiguration figure 95 shows a power supply configuration where all 1.8 v v oltage rails are powered by external supplies. the ldo_en pin is left floating, and all of the internal ldos except dvdd18v are disabled. the transmit dac, a uxiliary converters and i/o pads run from a 3.3 v supply. 3.3v 1.8v ad9961/AD9963 08801-180 aux33v ldo_en rx33v rx18v rx18vf clk33v dvdd18 dll18v clk18v dr vdd txvdd figure 95 . 3.3 v and 1.8 v s upply configuration power dissipation the ad9961/AD9963 power dissipation is highly dependent on operating conditions. table 30 and figure 96 to figure 103 show the typical current consumption by power supply domain under different operating conditions. the current draw from the 1.8 v supplies are independent of whether they are supplied by the on - chip regulators or by an external 1.8 v supply. the quiescent current of the ldo regulators are about 100 a. the current drawn from the aux33v supply by the a ux iliary adc is typically 350 a. the 10 - bit auxiliary dacs each typically draw 275 a from the aux33v supply. the 12 - bit auxiliary dacs typically draw 550 a each from the aux33v supply. datasheet.in
ad9961/AD9963 rev. 0 | page 56 of 60 20 30 40 50 60 70 80 0 20 40 60 80 100 f adc (mhz) i rx (ma) rx18v rx18vf 08801-181 figure 96 . i rx18v and i rx18vf vs. f adc , both adcs enabled f dac (mhz) i txvdd (ma) 6 10 14 18 22 26 0 25 50 75 100 125 150 175 i fs = 4ma i fs = 2ma i fs = 1ma 08801-182 figure 97 . i txvdd vs . f dac , fsc = 1 ma, 2 ma, 4 ma, txvdd = 3.3 v f dac (mhz) i txvdd (ma) 6 8 10 12 14 16 18 0 25 50 75 100 125 150 175 i fs = 4ma i fs = 2ma i fs = 1ma 08801-183 figure 98 . i txvdd vs . f dac , fsc = 1 ma, 2 ma, 4 ma, txvdd = 1.8 v 4.0 4.5 5.0 5.5 6.0 6.5 7.0 0 25 50 75 100 125 150 175 f clk (mhz) i clk18v (ma) 08801-184 figure 99 . i clkvdd18 vs . f clk 4 6 8 10 12 80 140 200 260 320 f dll (mhz) i dll18v (ma) f clk = 50mhz, n = 1 f clk = 20mhz, n = 1 f clk = 20mhz, n = 5 08801-185 figure 100 . i dll18v vs . f dll , f clkin = 19.2 mhz, 30.72 mhz f rxd at a (mhz) i dvdd18 (ma) 0 4 8 12 16 20 0 25 50 75 100 125 2x 1x 08801-186 figure 101 . i dvdd18 vs . f rxdata , 1 , 2 (rx o nly ) datasheet.in
ad9961/AD9963 rev. 0 | page 57 of 60 f dac (mhz) i dvdd18 (ma) 0 20 40 60 80 100 0 25 50 75 100 8x 4x 2x 1x 125 150 175 08801-187 figure 102 . i dvdd18 vs . f dac , 1 , 2 , 4 , 8 (tx only) 0 5 10 15 20 25 30 35 0 10 20 30 40 50 60 70 80 90 100 f dat a (mhz) i dr vdd (ma) 3.3v 2.5v 1.8v 08801-188 figure 103 . i drvdd vs . f data , (tx enable and d isabled) power calculation example the following example shows how to estimate the device power c onsumption under a typical operating condition . operating c onditions: f clk = 60 mhz f dll = 120 mhz f dac = 120 mhz f adc = 60 mhz 4 i nterpolation 2 d ecimation dac full - scale current = 2 ma txvdd = clk33v = aux33v = 3.3 v aux iliary adc e nabled all other s up plies powered from external 1.8 v supplies. table 30. example power supply currents supply typical current (ma) typical power (mw) rx18v 74 133 rx18vf 30 54 txvdd 16 53 clkvdd18v 5.2 9.5 dll18v 7.5 13.5 dvdd18v (rx) 9 16.2 dv dd18v (tx) 35 63 drvdd 5 9 aux33v 0.5 1.7 total (1.8 v) 169 298 total (3.3 v) 16 55 datasheet.in
ad9961/AD9963 rev. 0 | page 58 of 60 outline dimensions compliant to jedec standards mo-220-vnnd-4 073108- a 0.20 ref 0.80 max 0.65 ty p 1.00 0.85 0.80 0.05 max 0.02 nom 1 18 54 37 19 36 72 55 0.50 0.40 0.30 8.50 ref 7.10 bsc sq exposedp ad (bot t om view) top view 9.75 bsc sq 10.00 bsc sq pin 1 indic at or sea ting plane 12 max 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 0.50 bsc pin 1 indic at or coplanarit y 0.08 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 104 . 72 - lead lead frame chip scale package [lfcsp_vq] 10 mm 10 mm body, very thin quad (cp - 72 -4) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9961bcpz ?40c to +85c 72- lead lead frame chip scale package [lfcsp_vq] cp -72 -4 ad9961bcpzrl ?40c to +85c 72- lead lead frame chip scale package [lfcsp_vq] cp -72 -4 AD9963bcpz ?40c to +85c 72- lead lead frame chip scale package [lfcsp_vq] cp -72 -4 ad996 3bcpz rl ?40c to +85c 72- lead lead frame chip scale package [lfcsp_vq] cp -72 -4 ad9961 - ebz ?40c to +85c evaluation board AD9963 - ebz ?40c to +85c evaluation board hsc- dac - evalcz ?40c to +85c pattern generation and capture card 1 z = rohs compliant part. datasheet.in
ad9961/AD9963 rev. 0 | page 59 of 60 notes datasheet.in
ad9961/AD9963 rev. 0 | page 60 of 60 notes ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08801 -0- 7/10(0) datasheet.in

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